Yet another DIY GPSDO - yes, another one

[MIS42N]

That PIC has a 4 cycle instruction time so the 1pps output could be anywhere in a 400ns window. You would get within 100ns using an ATTiny for the same money. And yes I looked at Wikipedia before but it says nothing useful.

[AndrewBCN]

That PIC has a 4 cycle instruction time so the 1pps output could be anywhere in a 400ns window. You would get within 100ns using an ATTiny for the same money.
...

No, please check again the PIC datasheet (I posted a link to it): "- All single cycle instructions except branches."
In that respect, the ATTiny and the PIC 12F675 are similar. More importantly, the PICdiv code is of excellent quality and it implements synchronization. The AVR code is mediocre and I don't think it implements synchronization. So PICdiv it is.   

...
The pic is clocked by 10MHz (10MHz is fed from the OCXO into the pic's master clock). Everything inside the pic happens on the rising edge of its clock and the added jitter of the pic's 1PPS output is in XX pico-seconds area, afaik.

The PICs are on their way and I'll be sure to check and compare the 1PPS output from the PICdiv to the 1PPS output from the GPS (using probe cables of the same length and impedance!).

[iMo]

The "PICdiv" chip (maybe 20 types afaik) "dividers" are pre-programmed such they produce an output signal, where the "4 clock cycles per instruction" are already incorporated into the stuff.
Therefore take it as a dumb logic circuit - a divider by N - where only a rising edge of the input/output clock plays a role in this specific app.
http://www.leapsecond.com/pic/picdiv.htm

Jitter is extremely low since the PIC is a synchronous device. Recent measurement suggest it is less than 2 ps.

[MIS42N]

No, please check again the PIC datasheet (I posted a link to it): "- All single cycle instructions except branches."

Please check the data sheet more thoroughly. In section 10.0 INSTRUCTION SET SUMMARY "One instruction cycle consists of four oscillator periods". Also note "For external interrupt events, such as the INT pin, or GP port change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs". That throws another 400ns uncertainty into the mix.

I have been programming 8-bit PICs for over 10 years. I know how they work.

[thinkfat]

No, please check again the PIC datasheet (I posted a link to it): "- All single cycle instructions except branches."

Please check the data sheet more thoroughly. In section 10.0 INSTRUCTION SET SUMMARY "One instruction cycle consists of four oscillator periods". Also note "For external interrupt events, such as the INT pin, or GP port change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs". That throws another 400ns uncertainty into the mix.

I have been programming 8-bit PICs for over 10 years. I know how they work.

But it is irrelevant. Just don't use interrupts and you can exactly calculate how many clock cycles any piece of code will take.

[iMo]

The PicDIV's dividing by N works as a state machine clocked synchronously by the master clock (the clock coming from 10MHz OCXO, for example). Thus the 4_clock_per_instructions issue does not apply here.

It would apply when you try to divide by small N , like N=2,3,4,5 etc, where the "4 clocks per instruction" is the limiting factor.

Also - any messing with async signals at GPIO inputs could have a latency of many clocks - based on whether there are synchronizers at the inputs, etc., etc.
For example the "Sync" input - it should synchronize the divider to the rising edge of the Sync signal. That could be a subject to the 4++ clocks uncertainty, imho.

[MIS42N]

But it is irrelevant. Just don't use interrupts and you can exactly calculate how many clock cycles any piece of code will take.

I made the comment because the picDIV programs that were mentioned do use an interrupt for sync. So not irrelevant in this context. And why people use code for delays is a mystery to me. There are timers to do that.

[iMo]

I think the "Arm" and "Sync" signals there are used for not_timing_critical processes, like to reset the 1PPS signal to log1 in order to prepare a measurement waiting on the next 1PPS rising edge. Thus there is no need to wait 1 second worst case. It does not matter whether it takes 10us or 1ms.
Otherwise, while not using the Arm and Sync inputs, it works like a dumb divider by large N..

[MIS42N]

I had an overnight think about generating the 1pps from a PIC. If you just want 1pps that isn't aligned to anything, then no problem.

If you want to align the 1pps with something (e.g. the UTC second) then it is necessary to decide what is an acceptable error. There will be an error, just a matter of deciding how much is tolerable.

I think 1us can be achieved just by using the picDIV arm/sync and not actually monitoring the generated 1pps. It may a few hundred ns off due to the instruction time/interrupt latency issue. But if your aim is 1us then no problem.

To get within 100ns will require monitoring the output. If trying to align with the 1pps from the GPS, imho monitoring the falling edge of the PIC would be advisable. It is guaranteed to be a fixed time after the rising edge, and the processor may be busy dealing with the GPS rising edge so not able to attend to the PIC rising edge at the same time. To align within 100ns, just change the OCXO frequency for a few seconds. A shift of 0.25Hz will reduce the error by 25ns per second. I think your circuit will allow this. The Lars circuit won't allow it because it is locked to 10 cycle intervals.

Getting below 100ns is tricky and probably not worth the trouble, it requires the phase of the OCXO to be adjusted relative to the GPS 1pps. This depends on how your detector works. The Lars circuit does allow the phase of the OCXO to be shifted relative to the 1pps, but can't overcome the multiple 100ns cycle offsets.

[cdev]

This is what he's getting at and I am hoping to do this too in a project I am working on. I already have the GPSDO its planned to complement and a case with power supply and lots of BNC connectors and a rack mount chassis with a nifty alphanumeric display.

This is @tvb 's web site. He has a lot of info there. The most compelling reason is the synchronous nature of the PICS and the code which means no additional error is introduced.

http://www.leapsecond.com/pic/picdiv.htm

[MIS42N]

This is what he's getting at and I am hoping to do this too in a project I am working on. I already have the GPSDO its planned to complement and a case with power supply and lots of BNC connectors and a rack mount chassis with a nifty alphanumeric display.

This is @tvb 's web site. He has a lot of info there. The most compelling reason is the synchronous nature of the PICS and the code which means no additional error is introduced.

http://www.leapsecond.com/pic/picdiv.htm

Please read previous comments from #186 onward. We've all been there.

[AndrewBCN]

...
This is @tvb 's web site. He has a lot of info there.

Indeed it's a fascinating website by a true time-nut (by his own admission). The information about the PICdiv operation can be found in the source code, which is abundantly commented.

The PicDIV's dividing by N works as a state machine clocked synchronously by the master clock (the clock coming from 10MHz OCXO, for example). Thus the 4_clock_per_instructions issue does not apply here.

The frequency division is perfectly synchronous so indeed there is < 1ns jitter introduced by the PIC.

For example the "Sync" input - it should synchronize the divider to the rising edge of the Sync signal. That could be a subject to the 4++ clocks uncertainty, imho.

Yes, you are 100% correct. But I am thinking there are ways to work around that 400ns uncertainty, to get the PICdiv 1PPS perfectly aligned to UTC (within the limits of the GPS receiver, of course). Because it seems that the "uncertainty" is always exactly 100 or 200 or 300 or 400ns, so it's not an uncertainty at all, just a random exact time difference with only four possible values.
I will be testing that of course when I receive the PICs.
And here is where the STM32 GPSDO shines as an experimental platform and a source of fun. 

[AndrewBCN]

Hi,
I got some parts in the mail today:
1. 1N5711 Schottky diodes.
2. 1nF polystyrene capacitors, one of which was DOA!   
3. 10uH inductors.

The fast recovery Schottky diode and the polystyrene capacitor are required by Lars' 1ns resolution phase detector and the 10µH inductors are used in a T-filter to get an approximate sinewave 10MHz fundamental, for people who need/want a 10MHz sinewave (since the STM32 GPSDO uses a square wave OCXO).

I'll be testing/experimenting these circuits and posting some DSO captures in the coming days. I hope I can reproduce Lars' 1ns resolution measurements, but we'll see. 

[iMo]

That 10uH inductors are not optimal for 10MHz usage (ie a filter). Something like a small T-37-2 (red) amidon iron powder toiroid would be a better choice..
~50turns for 10uH..

[AndrewBCN]

That 10uH inductors are not optimal for 10MHz usage (ie a filter). Something like a small T-37-2 (red) amidon iron powder toiroid would be a better choice..
~50turns for 10uH..

By not optimal, do you mean losses? Do they radiate the 10MHz signal? Or something else? I have very little experience with RF analog circuits.

[thinkfat]

I'd rather go for a 4th order Butterworth low pass. Should get you about 38dBc attenuation at 30MHz. Plenty of online calculators around that will get you the design. 50 Ohms output recommended. You'll need a driver.

[iMo]

Yours inductors are for general decoupling/blocking. They have got low Q and high temperature coefficient (ferrite core). Also they pick up noise (as a ferrite rod antenna).
The iron powder toroids are with low tempco, higher Q, and they are closed (toroid) for outside interference..

[AndrewBCN]

So I assembled the buffered (using a 74HC14) sine wave T filter using 2 x 10µH inductors + 1 x 100pF ceramic capacitor on a breadboard next to the STM32 GPSDO (which is also on a breadboard) and the resulting quasi-sine is rather acceptable imho. Yes, there is a certain amount of noise and depending on the application this may or may not matter. Also I am not sure how much of that noise is due to the breadboard assembly and would be avoided when the circuit is assembled on a proper PCB.

Next to be tested: Erik's version of Lars' 1ns resolution phase detector (the 74HC74, the Schottky diode etc can be seen on the same breadboard as the square to sine converter). And personally I find that a DSO is an essential tool to understand what is happening during these experiments.

Pics of the breadboard assembly and DSO traces (yellow is 10MHz square wave from OCXO, green is quasi-sine output of T filter):

[Johnny B Good]

I'd rather go for a 4th order Butterworth low pass. Should get you about 38dBc attenuation at 30MHz. Plenty of online calculators around that will get you the design. 50 Ohms output recommended. You'll need a driver.

 I went for a 5th order Butterworth as you can see in the hand drawn circuit diagram for the MK II design in reply #123, page 5 in this thread (https://www.eevblog.com/forum/projects/yet-another-diy-gpsdo-yes-another-one/msg3620946/#msg3620946 for those who prefer a quick link    ).

 I tracked down a filter calculator here: http://leleivre.com/rf_butterworth_LPF.html and selected the 5th order LPF option using a 12MHz turnover to reduce the 3dB attenuation at 10MHz, further boosting the output by resonating the C3 cap with a 1.6μH inductor (L3) in parallel.

 I'd needed an inductor to ground reference the output anyway and this seemed a cheeky way to achieve that and compensate for the loss when operating so close to the turnover frequency to maximise attenuation at the 3rd harmonic and beyond. ISTR achieving a 50dB attenuation of a 30MHz sine wave compared to 10MHz when checking its performance (with my much modified FY6600 "toy" function generator, natch  ) as a result of this addition.

 My first attempts using toroidal cores recovered from scrapped PC motherboards produced very poor performance (barely 30dB attenuation at 30MHz). In hindsight, a not too surprising result since I doubt rather think the buck regulator circuits they'd been part of would have been switching at sub MHz rates and an increased loss at 10MHz would be a switching noise reduction bonus in this service.

 In the end, I tracked down a collection of small inductors (VHF transistor radio chassis are a good source) wound onto open ferrite bobbins with black heatshrink wrapping that I could tune by unwinding turns whilst measuring with a cheap BangGood LC meter. These were a vast improvement over the ex-PC MoBo toroidal cores I'd tried. The last image in that post shows a fine example of the filter's effect on the 10MHz square wave output coming from the 74HC14 four gate buffer (CH1, yellow trace).

[thinkfat]

This is what I use. Components are all SMD 0805, though. Johanson Technology has a nice catalog of RF coils which are good to use for this kind of stuff.

[Johnny B Good]

 I'm still old skool when it comes to small diy projects like this and I tend to repurpose my collection of 'salvage' (where the components are still fit for their new purpose ).

 I've not yet gotten round to tooling up for diy multi-layer PCB layouts that I can submit to a PCB house upon which to solder a collection of brand new smd parts. Maybe one day soonish, I might make that leap but for now, my version of 'dead bug' on a copper clad board serves me reasonably well. However, I've taken note of your recommendation of  Johanson Technology as an RF smd inductor supplier for when I take that leap into the present day.

 That MK II was built onto such a copper clad board - seeing as how there were only 4 1/2 3 1/2 DiP IC's worth (plus OCXO) in that project, I just drilled 0.6mm holes to mount the ICs conventionally, chamfering all but the ground pin holes so I could connect using jumper wires on the underside to complete the circuit connections.

 If there had been just a few more ICs to mount, I'd have used the dead bug style of construction instead (and never mind its 'ugliness' - I see the beauty of "function over style" as an engineering statement anyway in these DIY builds).

 I noticed that your 4th order Butterworth LPF is only one small capacitor away from being a full blown 5th order filter which is a little surprising seeing as how this 'extra' takes up so little space. When I was considering my options, the even order filters struck me as being the less elegant asymmetric option (the expression "Being one sandwich short of a picnic." coming to mind in this case),

 Since the caps in my case are the smallest component parts when relying on thru-hole inductors, it just seemed a little remiss of me to save on the relatively minuscule space that one such extra capacitor would occupy so I "spared no expense" and went for the 5th order filter.

 One feature of low pass filtering a 10MHz square wave is the fact that the third (most troublesome) harmonic from the gate outputs is just one third of the fundamental's amplitude to begin with which is theoretically just over 9.5dB down (and likely a little in excess of 10dB down due to the limitations of the 74HC series of ICs at 30MHz). In this case, you can expect to see the third harmonic content down to 60dB below the fundamental at the output representing a THD of around 0.1% given that the higher harmonic contributions should disappear into the noise, assuming the filter is doing a reasonable job up to 100MHz and beyond. It's no wonder the sine wave looks 'perfect' on a scope trace!

[thinkfat]

5th order Butterworth is a clever thought as it is mostly symmetrical, saves on unique BOM items Only one inductor value needed and two different capacitors.

Your design however leaves me wondering, you go to some extent to achieve a 50 Ohms impedance and then you slap a crystal at the end of the filter. I understand that it's series resonance is really quite narrow and the gigantic Q of the crystal certainly doesn't present 50 Ohms outside of its passband, have you spent time investigating what this does to the characteristics of the filter?

[S57UUU]

I would suggest a Chebyshev filter. With a single frequency CW signal, ripple and dispersion are of no concern, while it is much steeper than Butterworth (lower order needed). Most filter calculators can do Chebyshev too.
Elliptic filters are even steeper, but I prefer Chebyshev for simplicity, and because the attenuation (theoretically) increases monotonically with frequency (lowpass).

Marko Cebokli

[iMo]

Also mind the output impedance of various cmos families and gate types vary from something like 15ohm up to 150ohm..

[Johnny B Good]

 That was the old, now stripped down MK I circuit, that I'd built onto stripboard. The MK II is the second circuit diagram below.

 The addition of the crystal was simply to filter out all the jitter components that were being injected from the Vcc and ground rails by all the additional TTL chips I'd used to convert the 13MHz OCXO's square wave output into a 10MHz square wave.  In that regard, it did clean up the output considerably. I wasn't overly concerned over any 'out of band' effect it may have had (I already had plans for the MK II by then and it was just a 'quick fix' anyway).

 The experience I'd gained with the MK I provided very useful guidance for the design and build of the MK II. Basically, it taught me how to avoid the errors and pitfalls created by the original design and build. In essence, whilst the use of a complex divide by 13 circuit (as clever as that may seem - I'd done it because I could) to pervert a 13MHz OCXO into doing duty as a 10MHz reference, it was not without its own unique problems of injected spurious noise onto the Vcc rail, made all the worse by by the use of stripboard construction.

 By sticking to a more conventional design (I had 7 examples of those ex-Symmetricom AE CQE 12v 10MHz sine output OCXOs to hand by then -close cousins of the original 13MHz OCXO I'd started off with), I was able to eliminate four ICs reducing it to just 3 1/2 IC's worth to drill 0.6mm holes for in the copper clad board I'd substituted for the stripboard used in the MK I. That meant I no longer needed a xtal filter in the MK II as you will see when to take a close look at the second, hand drawn, circuit diagram below the MK I's diagram.

 BTW, I still have that first filter in the pot of components recovered from the MK I since I'd had to build it as a unit part on a copper strip made from a piece of opened up half inch water pipe due to the lack of space to build it directly onto the stripboard which in any case makes for a lousy groundplane even at 10MHz, let alone all the odd harmonics that need to be filtered out. It might yet see use in another GPSDO but sans its xtal embellishment.