Why does it overshoot 600mV every time? (Control loop stuff)

[void_error]

I seriously don't know what I'm doing wrong. The circuit was inspired by prasimix's lab power supply and it's almost identical apart from the power stage and a few more things. Quick link to the original schematic here.

EDIT: I forgot to change the power transistors to TIP3055 and a few resistor values for the AC analysis but the results are the same.









I've also attached the LTspice .asc files.

[void_error]

Try adding some esr to your output cap.

It just makes things worse. Did a parametric sweep at 1V output with 1u 1m 10m 100m ESR values and the first three yield roughly the same result. With 100m the overshoot gets worse as well as the undershoot.

[void_error]

Increasing the output cap value to 1000u reduces the overshoot by 200mV. Even with an ESR of zero it's still 400mV regardless of the set output voltage. I wouldn't be surprised if the overshoot only happens in simulation.

[void_error]

As far as I understand from the original schematic it's supposed to smooth out the transition between CV and CC modes and it seems to do that. I tweaked the values over many iterations. In the simulations I posted above only the CV loop is active, the current limit is set to 8A.

Having played a bit more it seems that the 100 ohm BE resistors of the power transistors are the only things that have any impact on the overshoot.

[Jay_Diddy_B]

Hi,

This might help:



Consider this circuit. It is a simplified model of the circuit that you have. If the load current is high, then the two transistors work together as a Darlington. If the load current is low, Q1 can supply the load current through the B-E resistor of Q2. There is no Darlington action, Q2 collector current is zero. The voltage drop from Q1 base to the output is 2x Vbe at modest to high currents and 1x Vbe at very small currents.

This is why there is a 0.6V jump.

Jay_Diddy_B

[void_error]

Thanks. Somehow I overlooked that fact but I did suspect the problem wasn't related to the op amp control loop.

Is there any way to get rid of the 600mV overshoot?

[Jay_Diddy_B]

Thanks. Somehow I overlooked that fact but I did suspect the problem wasn't related to the op amp control loop.

Is there any way to get rid of the 600mV overshoot?

In some Agilent Power Supplies, the output stage has the ability to sink current, as well as source current. The reverse current can be 20% of the maximum output current, HP 6654A or as high as 100% in the 6632A/B.

The output stage looks very similar to a class AB audio amplifier, but it is asymmetric.

The ability to sink current, helps when you turn the voltage down. They call this down programming.

Jay_Diddy_B

[void_error]

So what I have to do here is design an asymmetric class-AB output stage?

I'll try to find some schematics for the power supply you mentioned.

[void_error]

It seems to reduce the settling time but it's still too slow. How can I make it faster?

[void_error]

Changing the power transistors to something faster improved the overshoot a bit, it's only 400mV now.
Maybe a load step from 0.1% to 100% and back to 0.1% is a bit too harsh?
Anyway, here are the results:

[Kleinstein]

Having a push pull output stage helps a lot, as it avoids having the output stage in a slow low current mode. The improvement might not be that large for the transient test shown, but without a 2 quadrant output stage there are essentially always troublesome cases.
It also helps to have the fast local feedback an the transistor level not directly from the output, but separated from the output by a low inductance resistor. This could be the emitter resistors for load sharing / bias current adjustment. This way the local loop can be faster as it is not seeing possible extreme pure capacitive load.

For the output capacitance a combination of capacitance with very low ESR and some with ESR is good. The low ESR part for the very fast transients (e.g. << 1 µs) and the ESR part to help with stability of the loop. The capacitance is essentially the only thing to limit the drop until the transistors can respond.

A fast output transistor also really helps - there are fast audio grade BJTs, like 2SC5200, about 10 times faster than the 2N3055. However parasitic inductance might be limiting earlier. So there are limitation to what is possible in real life. Low impedance at high frequency means that even small (e.g. 10s of nH) parasitic inductance can be important.

For the simulation I would start with just 1 transistor and add parallel one later - it is less confusing and easier to change.

[void_error]

I'll get back on it and play with a single output transistor with a ~2A max current limit. I noticed the settling time gets worse at lower output voltages which is a problem so I'll try sinking the current into the negative -5V rail.

One thing I forgot to mention is that at 40V output the current will be limited to 4A, it'll only go up to 8A at 20V output or less, achieved with a switchmode pre-regulator simulated here using E1 & V3.

[void_error]

Adding ESR to the output caps made the whole thing oscillate so I had to tweak R54 & C12 to make it stable again.
Sinking current to -5V improved the recovery time in case of low output voltages. Current load step is between 1.875mA and 1.875A.
Can I make it behave better or am I pushing it?