Analog Multiplier/Divider

[tree]

Hello folks,

I've been working on an analog multiplier/divider and finally got around to properly building it, testing it, and documenting it.

I've attached the schematic, formulas, and a simulation file. I didn't include the derivation, but for those who want it, I'll post it.

I didn't have the simulation models for the matched NPN transistors (MAT12), so I used two different NPN transistors to show the effects of matching. To a first order, the temperature coefficient is ZERO for two reasons, 1. VT (thermal voltage) cancels out 2. the IS (saturation current) which has a temperature dependence also cancels out. The Early effect will cancel as well to a first order.

I performed some DC tests using my Agilent U1272A and Agilent 34461A DMMs and have confirmed that it is indeed accurate to within 20mV at the output when multiplying 6V and 2V. I don't have enough time to post more test results simply because I'm too lazy to take pictures/screenshots. Hopefully soon. I have no idea what the bandwidth of this circuit is simply because I haven't measured it. The MAT12 matched transistors have a GBWP of 200MHz which should provide enough bandwidth for MOST applications. The limiting factor in this case is the op amp (LTC1151) which has a GBWP of 2MHz, but a fast op amp can be substituted. I used the LTC1151 because it has sub-uV voltage offset and a bias current of 300pA (Ib + Ios) at room temperature.

[tree]

NOTE: This is only a single-quadrant multiplier, but with the proper signal conditioning, this can become a 4-quadrant multiplier.

I've also replaced the matched BJTs with 3904s and some quick measurements have shown that the output is within 3%, so for those who don't want to spend $30 on MAT12 matched pairs, you could replicate this circuit with common BJTs. You could probably get the error even lower by hand matching the transistors, although I haven't tried yet.

Stay tuned for measured data!

[zapta]

Can you give a high level explanation how it works?

[tree]

Can you give a high level explanation how it works?

V1 across R1 and V2 across R2 create a current. Then Q1A and Q2B convert that current into a voltage with the help of the inverting op amps. This is essentially a logarithm function (see Ebers Moll model), but for the most part the '1' in that equation can be disregarded.
It performs the sum of two logarithms which is essentially the logarithm of a multiplication by using Q1A and Q2B Vbe voltages. The sum of their base voltages shows up at pin 7 of U2B. As you can see, it is beginning to look like a multiplier. V3 provides a reference voltage for division which is really a feature of the circuit. Q2A is necessary to cancel out the effects of Is. Then an anti-log is performed by Q1B and its associated op amp, which now results in equation 2 (see formulas PDF).

I hope this makes sense.

[tree]

I've taken some preliminary test data providing the test voltages (V1 and V2) using a linear power supply. I was too lazy to do a proper setup with voltage references but it does give a pretty good idea of how accurate this is. I did however manage to use a voltage reference for V3 by using a voltage reference, a 10turn pot and another LTC1151 as a buffer. I measured all these values using my 34461A 6.5 digit meter. My night here is coming to an end so I had to rush these measurements!

[tree]

So this morning I got up and finally used voltage references to test the multiplier.
I only made 10 measurements, but it shows that the error is a bit less overall than my initial test. It also shows that the error rises when multiplying very low level signal in the tens of mV.
The error seems to be less than the 0.5% transistor matching, so I'm quite happy. Stay tuned for data using unmatched 3904s.

I believe the reason why the error increases at low levels is due to the low current level. 10mV across 100k is 100nA. Leakage and bias currents are enough to create large enough errors. I think if I used 10k input resistors instead, that I might be able to lower the error when multiplying tens of mV.

[jeremy]

very interesting, thanks for sharing!

[T3sl4co1l]

Cool!

Now build a synth or something around a few of them

[tree]

Cool!

Now build a synth or something around a few of them

I haven't even considered all the possible applications. I designed this because I wanted to be able to monitor power for whatever reason and felt like getting a multiplier/divider IC would be cheating myself.

[BravoV]

Cool thread, always curious how an analog mul/div circuit is made from discrete components, subscribed, thanks ! 

Edit : I can see you're using ltspice for simulation, please attach the zipped .ASC ltspice simulation file too.

[tree]

Cool thread, always curious how an analog mul/div circuit is made from discrete components, subscribed, thanks ! 

Edit : I can see you're using ltspice for simulation, please attach the zipped .ASC ltspice simulation file too.

I tried to, but I couldn't upload ASC files. Well, I changed the extension to TXT, so once you download it, manually change the extension back to ASC.

[tree]

What I've learned so far: If you need a multiplier/divider, buy the darn IC because it's far cheaper than what I made. The matched pairs are $30 each, op amps at ~$12 each, and the resistors are quite cheap. At the moment I'm testing how accurate the circuit is using unmatched 3904s and so far the error is around ~1% max. The problem I do however see is terrible output fluctuation. Even though the inputs are stable, the output fluctuates a lot which makes it very difficult to get an accurate reading. This is where my 34461A comes in handy with its fancy statistics features. I take about 1000 readings at 10PLCs at 6.5 digits and then get the average value.

[T3sl4co1l]

Partly for S&G, I once build a two quadrant multiplier -- an OTA.  I added a sampled servo loop, so that, for 10us out of every 10ms, the +in is switched to zero, the output is switched to an error amplifier, and the error amplifier is switched to a sample-and-hold on the -in.  So in the 10us, it settles to zero offset, then resumes normal operation at some new -in offset, where it can drift around some more, then get reset again.

To get 100% uninterrupted service from such a circuit, you need exactly double everything: two OTAs, so one handles the signal while the other gets autozeroed.  PITA.  Useless.

The alternative is a circuit which does not suffer from offset voltage and thermal drift: a proper LM13700 or whatever.

On the upside, the performance was astonishing.  I could literally bring one transistor (in the diff pair) up to soldering temperature -- the offset was something ridiculous like 1V -- but it was still multiplying just fine, understanding that since absolute temperature was different, the gain was proportionally different as well.  I also tried it with germanium transistors, which also worked just fine, until the heated transistor got so hot it literally became a three-way short (so much leakage between B/C/E that it looks more like a crappy resistor than any kind of transistor).

It also compensated for drift in the current mirror transistors (which were doing level shifts, not a key part of the circuit behavior).

Tim

[tree]

I've substituted 3904s for the matched pairs and performed 10 tests using approximately the same input signals as last time and have shown that the matched pairs do perform better, but that was to be expected. What I didn't expect however is for the output to fluctuate A LOT using 3904s in the circuit. I presume that is due to the fact that the actual transistors are not on the same die, so they are not thermally matched. They were mounted approximately 2cm away from each other. The very small thermal gradient and air flow over them causes their Is and VT terms to fluctuate which doesn't result in perfect cancellation. If the transistors were on the same die, but did not have Is match, the fluctuations would have been much less, although still present. The Is term is temperature dependent and not matched so the output would fluctuate with time.

Here is a list of tests I intend to perform:
1. 1% resistors and matched pairs
2. 5% resistors and matched pairs
3. 0.1% resistors and 2222 transistors
4. low level input signals using 10k 0.1% resistors and matched pairs

[tree]

Partly for S&G, I once build a two quadrant multiplier -- an OTA.  I added a sampled servo loop, so that, for 10us out of every 10ms, the +in is switched to zero, the output is switched to an error amplifier, and the error amplifier is switched to a sample-and-hold on the -in.  So in the 10us, it settles to zero offset, then resumes normal operation at some new -in offset, where it can drift around some more, then get reset again.

To get 100% uninterrupted service from such a circuit, you need exactly double everything: two OTAs, so one handles the signal while the other gets autozeroed.  PITA.  Useless.

The alternative is a circuit which does not suffer from offset voltage and thermal drift: a proper LM13700 or whatever.

On the upside, the performance was astonishing.  I could literally bring one transistor (in the diff pair) up to soldering temperature -- the offset was something ridiculous like 1V -- but it was still multiplying just fine, understanding that since absolute temperature was different, the gain was proportionally different as well.  I also tried it with germanium transistors, which also worked just fine, until the heated transistor got so hot it literally became a three-way short (so much leakage between B/C/E that it looks more like a crappy resistor than any kind of transistor).

It also compensated for drift in the current mirror transistors (which were doing level shifts, not a key part of the circuit behavior).

Tim

Do you think that the germanium transistors had lots of leakage because of their lower band gap compared to silicon?

If you have the schematic, I'd love to see it!

[T3sl4co1l]

Yes, the behavior is sorta-kinda proportional to bandgap / temp.  So germanium at room temp is about as leaky as silicon at high temp (say 100-150C?), and at high temp, it goes metallic (band gap ~filled with thermally generated pairs) and acts like a three way resistor.  Which silicon does at ~300C or something like that, or SiC at ~500C, etc.  Likewise, chalcogenide semiconductors like PbHgTe etc. have a very small bandgap, acting ~metallic at room temperature, and requiring refrigeration to do interesting semiconductory things.

Hmm, 'fraid I don't have the schematic handy.

Tim

[tree]

I've gotten around to doing some more testing using 1% 100k resistors and the matched pairs.

[KerryW]

You could try a DMMT3904 matched pair of 3904s on a single die.  Matched to 1% typical, 2% max.  $0.40 from Mouser.

[T3sl4co1l]

None of the dual transistor devices are single die.  If they were, you'd know it by the price and availability.

In fact, the thermal matching isn't even much better than loose discretes, something like 150 C/W differential.  The leadframes are not common (for obvious reasons), and the encapsulant doesn't buy much conductivity.

Some are specified for current mirror operation; those are rated for regions of runaway (where the collector voltage and current on the 'output' side causes that junction to overheat and exceed either a certain matching tolerance, or runaway altogether).  A three transistor (e.g. Wilson) mirror is preferred for these purposes.

Tim

[atferrari]

None of the dual transistor devices are single die.  If they were, you'd know it by the price and availability.

In fact, the thermal matching isn't even much better than loose discretes, something like 150 C/W differential.  The leadframes are not common (for obvious reasons), and the encapsulant doesn't buy much conductivity.

Some are specified for current mirror operation; those are rated for regions of runaway (where the collector voltage and current on the 'output' side causes that junction to overheat and exceed either a certain matching tolerance, or runaway altogether).  A three transistor (e.g. Wilson) mirror is preferred for these purposes. Tim

Consecutive dies in the wafer if I understand it right.