Whining boost converter, compenstaion network, ltc3124

[Artlav]

I want to make a boost converter with LTC3124, which would power a 5V device from a couple of supercaps.
1MHz switching frequency, Vout of 5V, 100mA output current
There is an example circuit for just that in it's datasheet.


I rounded up some of the component values, and ended up with this:


I tried to follow it's PCB guidelines, but since i can only make 2 layer boards, it's probably not perfect.




It works great for the most part. The resistor divider is somewhat moisture sensitive, but that's solvable with coating.

Problem is in how much of a "most" it is...

Once the input voltage gets above 4.4V, the thing starts whining and the chip heats up noticeably.
Considering that this is the area where it would be operating for 99.9% of time, that's not good.
The whine gets better close to 5V, and it works just fine, but it still looks and sounds wrong.
At higher currents, around 500mA it goes from being at 30*C to 70*C when the whine starts.


Now, there are two things i can think of.
First is the layout. I tied putting it on a single-sided board at first, and ended up with a roaring fiasco. This time around it works much better, but i can't really know if it's good enough.

Second is the compensation network, since i changed the component values a bit.
The pin 9, Vc, is supposed to have something called a compensation network connected to it.
There are several pages of mathematics in the datasheet on how to compute it, and i tried to follow it.

However, i can't get the numbers they are getting in the examples provided.
Probably because there are also several things i have to pick with no guidelines what-so-ever on how - the crossover frequency and the phase boost of the filter poles.

I don't think i understand the concept.
Can it be the problem, and if yes - how can i figure out how it works?

[bktemp]

Your GND connection at PGND and SGND is not the best.
PGND must have the shortest possible path to GND, otherwise the efficiency will be bad.
Everytime the boost transistor switches, the parasitic inductance from PGND to GND will generate a offset voltage. Since SGND is directly connected to PGND, it will also be effected.
Cin, Cout and PGND should be as close as possible.

[T3sl4co1l]

Hmm, CIN should've been placed right between pins 4-5, and CVCC by pins 4 / 6-7.

Why the long bottom trace to pin 11?  That should'be been done on the top... routing it on the bottom makes a cutout in the pour, which frustrates the current path from the single via at CIN over to the single via at the IC ground.  If that trace had been shorter, or the trace by R2 moved to the opposite side of R2, the ground pour would've connected around it, which would probably help.

Also, that trace going from RT to R2 is just more ground, right..?  Why?  Avoiding ground loops?  (Honestly, probably not a bad idea.  But there may be RF currents disturbing it, which could make it even worse, too.  Does the datasheet give any indication what the rise/fall time on this thing is..?)

Top side pour would be good too.  Load that thing up with as many vias as you care to insert!

Regarding ground loop, if you place CIN, CVCC, the top half of the IC (pins 1-5, 13-16), C1 and COUT as close as possible, grouped together on their side, then no power currents flow on the signal side (pins 6-12) and the control loop should be happy.

As for where you're at now... dunno, maybe increase CF to 100 or 220pF?  Add a small cap (10p to 220p) across R2?  Short that isolated ground to the pour?  Try adding more vias off the tips of pins 2, 4?

Tim

[Artlav]

As for where you're at now... dunno, maybe increase CF to 100 or 220pF?  Add a small cap (10p to 220p) across R2?

I forgot to say - the reason i suspected the "compensation network" is that touching that pin with a finger fixes the problem.

Tried changing CF to more, much more, and less - not much improvement. Much more makes it worse, actually, and less makes no difference.
100pF was the best - it limited the the whine to the area between 4.4V-4.6 V.

Adding any cap across R2 makes it go bananas.

Since SGND is directly connected to PGND, it will also be effected.

Perhaps, but that's exactly what the reference layout in the datasheet looks like.

Why the long bottom trace to pin 11?  That should'be been done on the top...

Exposed pad under the IC makes that kinda hard.

Also, that trace going from RT to R2 is just more ground, right..?  Why?  Avoiding ground loops?

Signal to signal, power to power, as datasheet suggested.
Without that it does not work at all, i tried.

Load that thing up with as many vias as you care to insert!

That's a alot of manual labour...

[bktemp]

Since SGND is directly connected to PGND, it will also be effected.

Perhaps, but that's exactly what the reference layout in the datasheet looks like.

It may look like so, but there is a big difference:
In the reference design, SGND and PGND do not share a single via. SGND and PGND are connected into a massive GND layer and this is connected using several vias to the other GND planes.

The datasheet suggests a 4 layer board. Your board has not even 2 fully usable layers. High frequency + high currents require a very good layout with massive via stitching to reduce all parasitic inductances as good as possible. This may not be possible with a simple home made board.

[georges80]

Yes, your layout is nothing like the 4 layer design in their datasheet.

If you think adding a bunch of vias under the chip is "a lot of manual labour" then you have an interesting attitude to doing design.

These kind of high frequency switching controllers need very careful attention to the switching currents that are present and where they are flowing.

Your pcb layout is more a DC connection of signals without consideration for the AC currents and how they 'bounce' the ground. I've designed quite a few high power LED drivers with various LT components and somethings you MUST use 4 layer boards to isolate the power ground from the signal ground. Signal ground is common to the various compensation/sense/etc components that need signal grounds and that ground does NOT have switching ground currents flowing through it.

What you are hearing and feeling (overheating) is the switcher running into stability issues. Fiddling with external component values (compensation caps etc) are bandages on a massive hemorrhage (your poor PCB layout). Maybe you'll get it to work, but more likely there will be various operating points (different Vin/Vout and Iin/Iout ranges) where it will misbehave again.

You need to FIX your layout!

cheers,
george.

[T3sl4co1l]

Why the long bottom trace to pin 11?  That should'be been done on the top...

Exposed pad under the IC makes that kinda hard.

Oh, so it is...

Well that definitely needs to be grounded too.  All the more reason for a top pour!

And...

Load that thing up with as many vias as you care to insert!

That's a alot of manual labour...

Yes, it is, and it's necessary, and the price you pay for hand made PCBs!

Ed: possible construction method to address this:
- Take off the IC
- Get some copper foil (e.g., peel some copper clad, shine up both sides?)
- Solder the foil onto the ground pad, so it extends out the ends
- Solder the chip back down
- Add vias to the now-extended pad "pour".

If you're feeling brazen, you might also add foil strips connecting the exposed pad to the ground pins, so everything can be "star grounded" (sort of) there.

Tim