Opamp based current limiter oscillates with inductive load

[brumbarchris]

Hi all,
I have to design a circuit that will limit the current through a solenoid to about 130mA. The solenoid has about 2mH inductance and a DC resistance that will vary between 5 and 15Ohm (depending mostly on temperature). The goal is to always charge the inductor to the same current, without worrying about timing or temperature. Hence, the need for a current limiter.

I have put together the attached circuit in LTSpice, using an opamp based current limiter circuit, in combination with a specific P channel MOSFET (the DMP10H400SE) selected so as to withstand the negative voltage pulse which appears when turning off the inductor).

Unfortunately, it oscillates. Quite ugly. The current limiting works when the load is purely resistive (with L_load removed), but it oscillates as in the attached plot when the inductor is in the circuit. Just to explain the V3 and M1 function: this has nothing to do with regulating the current, I just use that to turn OFF the main MOSFET very fast, as this is another requirement that I have.

I suppose the oscillating appears due to the horrible phase margin (or lack of, rather), but I must acknowledge my limits and ask for help with regards to how to fix/compensate and make it work. I have attached both screenshots and the actual LTSpice files, for whoever would be kind enough to spare some time, the subject is not trivial (at least for me, I know there are many thick and heavy books written on the subject). All files need to be kept in the same folder for the simulation to run.

In the attached simulation, the current is supposed to flow through the load for 2ms, between timestamps 5ms and 7ms.

Best regards,
Cristian

[MagicSmoker]

That wouldn't be my first choice of a constant current source to drive a solenoid*, but regardless, if you are seeing the current oscillate then the first thing I'd try is adding a series diode-resistor damping network across the solenoid (with the anode to ground). The resistor value isn't terribly critical as long as it is somewhere between 0.5x and 2x the characteristic Z of the solenoid and its oscillation frequency. Just eyeballing the circuit I'd say a resistance somewhere between 100 and 400 ohms should work, and a bonus of this modification is that the kickback from the solenoid will be reduced as well.



* - I'd likely go with a simple bjt current source with an LED for bias.

[brumbarchris]

We cannot damp the kickback for the solenoid, as that is the actual part we are interested in: we need to measure the big pulse which appears when turning off the current through the solenoid. Although, for the record, placing a 100Ohm resistor in parallel to the solenoid does indeed remove the oscillations.

Also, using a BJT based current source is a bit difficult, as we only have 5V available as a supply and the BJT takes a bit too much voltage drop to operate correctly.

These things aside, I would still like to understand why the current circuit does not operate with an inductive load. As I wrote above, removing the inductor completely (and leaving just the DC resistance of the solenoid) allows the constant current to correctly regulate to 130mA without oscillating. Bringing the inductor in the equation, for me would indicate that current through the load would vary slower, giving the opamp even more time to act. Unfortunately, I see quite the oposite in simulation, with the opamp not being capable of correctly regulating the gate of the MOSFET when I add the inductance. This is why I suspect is a "phase margin" kind of problem.

[MagicSmoker]

We cannot damp the kickback for the solenoid, as that is the actual part we are interested in: we need to measure the big pulse which appears when turning off the current through the solenoid.

Hmm. Should have made that more clear in the first place.

Also, using a BJT based current source is a bit difficult, as we only have 5V available as a supply and the BJT takes a bit too much voltage drop to operate correctly.

Try a PNP instead of a p-ch MOSFET as the output device in the same circuit, then. BJTs make vastly better current sources which reduces the amount of work the op-amp will have to do.

These things aside, I would still like to understand why the current circuit does not operate with an inductive load.

Probably Miller capacitance resonating with the load inductance. That is, Cgd of the MOSFET multiplied by the loop gain. Another plus for BJTs is they have lower parasitic capacitance in general.

Attempting to slug the response by throwing more capacitance between various nodes is likely to cause more or worse problems. I'd try adding a resistor from gate to source next. In fact, I just tried a few values and 390R improves behavior quite a bit. Also, I changed the maximum timestep to 100n which vastly speeds up the simulation without compromising the results (this isn't always the case).

[bostonman]

Try installing a 1M and capacitor (pF???) in series to ground between U3 and R2.

The problem is probably the time constant. The op-amp is trying to compensate too quickly and oscillating. This should pull these oscillations to ground and change the time constant.

[ajb]

Of course it oscillates.  The inductance causes a substantial delay between a change in the state of the op-amp's output and the amount of current that's flowing through the feedback resistor.  This means there's a substantial phase shift in the feedback loop, which decreases phase margin and leads to instability.  You'll need to compensate for that.

The conventional way to fix this would be to add a resistor between R1 and the opamp's inverting input, and then add a resistor and capacitor in series between the op-amp's output and inverting input.  That's shown here: https://www.electronicsweekly.com/blogs/engineer-in-wonderland/current-sink-stability-2015-10/

(That article discusses instability caused by MOSFET capacitance, but the principle is the same, just in your case the frequency of concern is much lower (mH of inductance versus pF of capacitance)

[duak]

Christian, the simulation shows that the circuit is working as a relaxation oscillator.  The time constant is L/R or 2 mH/(12R +10R) = 90.9 us.  This agrees with the simulation waveform.

AJB is quite right about the solution.  To stabilize the circuit I would:
1.) add a 10K resistor between the '-' input of U3 and the lower end of R1,
2.) add a capacitor between '-' input and the output of U3.  The time constant (RC) should be at least 90.9 us.  I would start with 10n and then increase it until the oscillation stops.

I would also disconnect M1 drain from where it is and connect it to the  '+' input of U3 as well as remove C1.  This will allow the opamp to close the feedback loop and not require it to sink 50 mA when the solenoid current is supposed to be zero.

When this is done, plot VOUT.  I think you will find the voltage is very high so you have to add a diode and resistor across the inductor to limit the peak voltage.

[brumbarchris]

Hello again. Thank you for the suggestions, they greatly improve things. But still not there yet. As suggested, I added the 10k resistor on the - input of the opamp, as well as the capacitor. I did have enough engineering sense to add these before, but I was actually connecting the capacitor to ground, not to the output of the opamp: that was obviously wrong. I guess this proves my limits...

Anyway, following your suggestions I connected them correctly and the result improved. I obtained further improvements by slightly increasing the resistor at the opamp output from 100R to 300R. That seems to be its sweet spot. Despite these improvements, however, there is still some ringing remaining on the current through the inductor waveform, when the current source is turned on (see attached plots). It seems I cannot fight these by adjusting the newly added resistor and capacitor, as further increasing the RC constant just affects the overall rise time of the current, without damping this... lets call it ringing (although it is probably still a phase issue related oscillation, rather than resonance related). And increasing the opamp output resistance even further leads to funny results... it turns the settling oscillations into one single bigger overshoot (plot3).

So there must also be some other button I need to press... but which one?

I'll also take on board the suggestion regarding the M1 drain connection, but I want to get rid of this ringing first.

Best regards,
Cristian

[Kleinstein]

A inductive load is the worst case for a current source. One last resort is adding a RC series connection in parallel to the load.
Given the relatively low current this could be something in the 1 K and 10 nF range.

It will alter the AC part of the current a little though.
It also helps if the MOSFET is not too large to limit the gate capacitance.

[duak]

Christian, I hadn't realized that the LTC1052 is a zero drift opamp.  It is a chopper stabilized device that may have some characteristics that make it a poor choice for this circuit.  I would try a different opamp, one that is not zero drift but still has rail to rail inputs and output.  I would also try changing the M1 drain connection to see what effect it has.

[brumbarchris]

Hi all,
I managed to get to a good point, by implementing the suggestions of several of you, see the attached circuit and plot of the load current.

One thing that was repeatedly advised was to add a damping circuit on the load. As the point of this circuit is exactly to generate that negative pulse, I would have liked to keep it as "pure" as possible. However, as it seems that subsequent signal processing of this negative pulse will also need some signal conditioning, I decided to "give in" and add a 1k resistor in parallel to it.

Another suggestion was the gate to source resistance added for the main MOSFET (U2). I used to have the R2 resistor in series between the opamp output and the gate of the MOSFET, but it was doing more harm than good this way (the whole circuit was VERY sensitive to its value, and changing it from 75Ohm to 100Ohm (for example) would make a huge difference with regards to the output oscillating or not or overshooting or not. Small margin is generally not a good thing, so then following your suggestions I moved the resistor to its new position between gate and source of the MOSFET, while directly connecting the opamp output to the MOSFET gate.

I also changed the opamp, indeed the LTC1052 was an overkill and I selected the much, much cheaper (and "general purpose" labeled) AD8541.

I guess these three main changes made the difference

One thing that duak suggested I cannot do: connect the drain of M1 to VREF. The purpose of M1 is to block the U2 main MOSFET super-fast, so moving it away from its current position would defeat its purpose.

Another modification I made was to add the diode in series with the load. It is cheaper to get a higher voltage rated general purpose diode than a higher voltage rated MOSFET. This will allow me to select a much cheaper MOSFET, as well as faster, I hope. I also adjusted the VREF voltage to limit the current at 100mA, instead of 130mA. Given the inductance of the load, this will keep the negative pulse below 100V in this configuration.

Of course, I am still left with the problem of the opamp output being short circuited to VBAT (through M1) while the current source is off. The opamp output is 60mA short circuit rated, and I also do not think it is a good idea to permanently drive it in short circuit; after all, the current source will spend more time in its OFF state, rather than in ON state. So I am currently thinking about a solution to this (it was not so much of a problem when I had the R2 connected in series between the opamp output and the U2 mosfet gate, but as I changed the connection of this resistor ... this opamp output shhorting became a problem).

Best regards (and thank you for your help so far),
Cristian

[duak]

Cristian, when U2 shuts off, the inductor will generate a negative voltage to try to maintain the current that is flowing through it.  In your latest circuit this voltage will be I * R7 = 100 mA * 1K0 = 100V.  If you are trying to minimize the discharge time, you must increase the value of R7.  This means you will need to find a FET with a greater BVDSS, not easy since it is PMOS.  Also, R7 takes some current from the load inductor.  If you move D1 to be in series with R7 but still have the cathode connected to the same node, it will conduct only when VOUT is negative.

You really must have a resistor between the opamp output and the gate of U2.  In the real world, many opamps will oscillate when trying to drive a capacitive load and it may not be predicted by simulation.

I think the high frequency oscillation may be caused by the combination of the inductive load, the drain to gate (Crss) and gate to source (Ciss) capacitances of FET U2.  You can try to reduce the effect of Crss by adding some capacitance across R2. Try 1000 pF to start.

[brumbarchris]

Yes, I really need and want the opamp output resistance to be there. However, if I add it, the whole circuit seems to be VERY sensitive to it, even if I use low values.
I've attached two figures. The first one shows the plot of the load current with the resistor set at 10 and 20Ohm, respectively. Huge difference, and that is for a relative minor resistance interval. Not really happy with it.

The second one contains a fundamental topology change: whereas I did add in this gate resistance between the VOPAMPOUT and VGATE nodes, I connected the C2 capacitor to VGATE instead of VOPAMPOUT. I guess I am a bit uncomfortable with 3.3nF connected directly to the opamp output, given all this talk about opamps not being suitable to drive capacitive loads. This yields better results provided that I decrease also the value of R2. If I keep it high at 10k, like in the first figure, then I get the all-familiar (ugly) oscillations (despite the damping resistor across the inductor). But if I lower R2, then it seems I can vary the gate resistor up to even 300Ohm without many drawbacks (except for the ugly "blip" occurring when the current source is ON, but that is not so bothering: except for not knowing the reason for it).

A capacitor across R2 does not seem to be doing much. If anything, if it too large (>2.2nF) it brings in some ringing on the load current, when the current source is turned ON.

Also D1 in the previous post I had was a bad idea, I was under the impression it would protect the MOSFET from the big negative voltage puls which appears when the current source is turned OFF, but of course it doesn't (it would only work if the voltage pulse was positive, which it is not, obviously).

[ocset]

Hi,
What about this for a solonoid driver for you......please tell if it is not to your spec, and i am sure that i , or others, will tweak it to suit...
Attached is LTspice and pdf schem

[T3sl4co1l]

Huh, why are C1 (in the first circuit) and V3 referenced to ground?  (Doesn't matter in SPICE, but a real, noisy source will mind.)

Also, does it have to be a high side driver?  Either way, your flyback signal is still beyond the rails, but it can help save on level shifting or N/P transformations (and in turn, confusions like C1 and V3).

Regarding stability, exact results depend on a lot of variables: the amp's response, the transistor capacitance, even the load's inductivity (which is probably a combination of distributed capacitance and lossy inductance).  If you can't test your SPICE models against the real parts to prove them, then you're better off setting up a general enough circuit that can be compensated on the bench by changing parts values.  (To that end, about all you'd need here is a resistor in series with C2, for a pole-zero compensator.)

You may also need/want some R+C across the output transistor, either D-S or D-G.  This adds some capacitance in parallel with the transistor's own capacitance, but makes it lossy, tending to dampen oscillation.  Specifically, lossy at the crossover frequency (which is in turn set by Z_load and Coss, and opamp GBW and compensation), so the exact value of R and C depend on the loop response.  Downside: the output impedance is affected, so that it has a more resistive characteristic towards the cutoff frequency.

Ultimately, this limits the bandwidth of the signal you're looking for.  This is inevitable: you can do better or worse with various circuits, and component choice, but you can't have -- and wouldn't want -- something with infinite bandwidth.

More generally, you may consider a circuit that's not trying to be an ideal impedance, but just starts out as whatever in the first place, and your signal is measured as a ratio of voltages or currents or impedances.  An impedance bridge, for example.

Tim

[brumbarchris]

What about this for a solonoid driver for you......

Also, does it have to be a high side driver?

Well, it has to be a source, not a sink. So high side driver is needed.

Huh, why are C1 (in the first circuit) and V3 referenced to ground?

What should I reference them to? Isn't ground supposed to be the most "solid" thing in the circuit?

You may also need/want some R+C across the output transistor, either D-S or D-G

Do you mean a R in series with a C, or a R in parallel with a C? In fairness, I tried a C in parallel to R2, did more harm than good.

I guess the only thing I am unhappy about now is the fact that I have C2 connected at the gate of the main MOSFET; whereas I guess it is good to prevent the opamp output driving the capacitance directly, most of the schematics I've seen around have that capacitance connected at the output of the opamp.

Anyway, I am planning on ordering the components and trying a real circuit this week. Who knows, maybe it will work better than in simulation. We all know about Murphy, but my boss also has a good saying: "we must also have good luck, from time to time" (I know, not a good engineering practice to rely on that!).

Regards,
Cristian

[T3sl4co1l]

What about this for a solonoid driver for you......

Also, does it have to be a high side driver?

Well, it has to be a source, not a sink. So high side driver is needed.

So it's a source because it's a source?  Or is there some other reason?

It could also potentially be a negative sink, still being common ground (if that's the underlying reason).  But that would involve the same annoying level shifting so it wouldn't help any.

Huh, why are C1 (in the first circuit) and V3 referenced to ground?

What should I reference them to? Isn't ground supposed to be the most "solid" thing in the circuit?

Ground is relative, as all voltages are.  The op-amp is comparing a reference voltage to a voltage drop across a resistor (which happens to be sensing output current, the intended variable).  That resistor is referenced to VBAT.  Likewise, the PMOS is referenced to its source, which is connected to VBAT, or something near it.

You may also need/want some R+C across the output transistor, either D-S or D-G

Do you mean a R in series with a C, or a R in parallel with a C? In fairness, I tried a C in parallel to R2, did more harm than good.

"+" means series; "||" means parallel.

I guess the only thing I am unhappy about now is the fact that I have C2 connected at the gate of the main MOSFET; whereas I guess it is good to prevent the opamp output driving the capacitance directly, most of the schematics I've seen around have that capacitance connected at the output of the opamp.

Yeah, don't do it that way, put an R in series with the C instead.  Works better than trying to compromise with the series resistance and FET capacitance.

This, plus a resistor in series with C:



Tim

[brumbarchris]

Thanks for the reply and suggestions.

So it's a source because it's a source?  Or is there some other reason?

The reason is that the signal of interest is the negative pulse generated by the inductor which appears when switching off the current through the main MOSFET. We find it much more convenient to have this referenced to ground than to VBAT, despite it being negative.

Best regards,
Cristian

[ocset]

What about the attached one?...give me a shout if you want more work on the overshoot  when it turns the solonoid on.
..or maybe it helps to have a bit more current when the solonoid is turning on...to overcome inertia?

[brumbarchris]

So, as advised, I referenced the + input of the opamp to VCC, (instead of ground) and I have also added the C1 and R11 circuit elements (see updated schematic). But no matter how far away I play with the values of these components (and others, like R4, C2, R2) I cannot get rid of the horrendous current blip through the load!

Not sure why this appears. If it were a phase shift problem, I would expect it to result in perpetual oscillations. As it only appears once, could it be resonance? Could it be some parasitic of the M1 mosfet (rather than the main U2 mosfet) causing it?

I've also attached the actual LTSPICE simulation, for whoever is interested in giving it a "hands on" (well, virtual, at least).

Best regards,
Cristian

[brumbarchris]

Hi Treez,
The schematic that you propose is OK, but:

1. It has the exact same problem as my own circuit with the current overshoot that appears when turning on the current source. This does not help and it is an un-wanted effect.
2. It has a considerably slower turn-off time compared to my circuit, I measured something in the range of 10us (vs the <100ns in my schematic)

Turn-off time was a goal I mentioned in my original post, although not explicitly mentioning a hard figure, sorry for not being clear enough:

Just to explain the V3 and M1 function: this has nothing to do with regulating the current, I just use that to turn OFF the main MOSFET very fast, as this is another requirement that I have.

Best regards,
Cristian

[ocset]

OK , the attached has no overshoot.

...ill work on the turn-off, i am sure you  appreciate, the only way to reduce the current in an inductor quickly is to quickly  put a big voltage on it.....so eg make the inductor discharge through a high voltage zener, etc.
The problem is that the voltage then on the VGS of the pfet may go above max limits.

[brumbarchris]

.so eg make the inductor discharge through a high voltage zener, etc.

We will have a 1k in parallel to the inductor. And we decided to also reduce the current through the inductor to 100mA, instead of 130mA. That will give us 100V negative spike, and the selected MOSFET is rated at that. In practice, we will probably keep the current even lower, at 90mA or so, to give us some margin, but for the sake of numbers, we'll keep it at 100mA in simulation.


Apart from these details, I am analyzing the changes you made to remove the overshoot. I must admit, I have quite some idfficulties in correlating the differences between the two schematics and the result (i.e. dissapearance of the overshoot).

Regards,
Cristian

[ocset]

i removed the overshoot by pre-conditioning the opamp so it didnt rail its output just before it is brought into regulation......as such, when it is called upon to get into regulation, its output voltage has less far to slew...and thereofre the overhsoot does not hapen......its more of a trick than a feedback loop mathematical thing....but it does the job.

There is a resistor there, and by the bjt conducting through it, the opamp gets fooled into a fake type of regulation, so its output doesnt get railed.

This is often a problem, with many circuits.......at first the regulation opamp output is railed, and has  a long way to slew to get into regulation, so you just trick it into haveing its output near the reguilation point....then it has less far to go, and so gets into regulation quicker...and so no overshoot.