Need to interupt a 12V relay control side with a 3V micro, safest way to do so?

[Ian.M]

That's right except you seem to have the MOSFET drain and source swapped.  A P channel MOSFET needs to be connected with its source positive otherwise its body diode will conduct all the time.

The NPN transistor emitter voltage cant rise above the base voltage unless the transistor is faulty (excessively leaky or shorted).  The only disadvantage is that all the MOSFET gate drive current + the pullup current + the tiny bit of base current has to go through the MCU I/O pin so its no good for fast switching applications with large MOSFETs (high gate capacitance).

[DrGeoff]

Or you could use a micro relay on your microcontroller output (suitable buffered if required) which provides a clean set of contacts to do whatever you like. As well as some degree of isolation.

[jnz]

Ok, so, I took Kalvin's two normally open and IanM's minimal parts designs and put them in sim. They all seem to work well, but I have a bit of confusion maybe someone could help me clear up?

In IanM's design, I'm seeing a LOT of current being sunk at my GPIO pin. Far too much really. For this project I will want to make my micro sleep and wanted the entire board to be under 1mA quiescent. So if I want to leave my interrupting transistor circuit "on" so that if the user presses the switch everything still works, I can't be wasting a lot of power on the BJT and the mosfet. There is maybe only one or two circuits I'd do this "constant" activation with, the rest can wait until I wake the circuit which means there is an infinite energy source plugged in.

Here is what I drew up for IanM's design (please excuse the terrible appearance):
  It's saying approx 124mA being sunk at the GPIO which is way beyond acceptable. Granted, I kind of used a generic MOSFET because my sim program doesn't have a huge library.

Here is what I got for Kalvin's middle example:

Still too high at 3mA after the NPN. I kind of don't really get that voltage divider as well. It's 10k up and 1k between the gate and collector. That's a voltage of 1.11ish from 12V. If mosfets run on voltage and 1.1V works well, can't I increase the resistors on both sides to something like 1.11v ish at less mA loss down stream of the NPN? It would really only also help to make that 1K from the GPIO a 10K, but now I feel like I'd be getting into the gain and that's not something I really understand. Can anyone explain how to adjust these resistors?

That 1.1V is just about the gate threshold at 1V. But the max for the gate is -12, so wouldn't -6 be a little safer to ensure the mosfet is going to react as it should?

I'm on-board with the idea of how high and low side drivers need P and N channel respectively. But the resistances and gain is still confusing me. If there is any info anyone can add I'd appreciate it great!

Thoughts?

[Ian.M]

Sorry about that. I forgot it needs an extra resistor to set the pulldown current. between the emitter and the GPIO.  Subtract Vbe from the 3.3V rail voltage to get the emitter voltage, then calculate the resistor to limit the current the GPIO sinks to an appropriate maximum.  N.B. there is NO base resistor.

That makes it less attractive as its now two resistors, two semiconductors, so you may prefer the simple MOSFET level shifter approach even though it needs a driver with a very low VGS threshold.  or even the conventional NPN in common emitter with a base resistor to the GPIO..

[Kalvin]

Hi jnz,

You can simplify my design a bit:

1. D1 is only used to protect the gate if there should be any voltage bumps in +12V power supply. You can remove D1 if the mosfet can tolerate easily -12V gate voltage and you can guarantee that +12V will not bump to, say +20V, during transients which might violate the maximum gate voltage.

2. You can also remove R2 if you remove D1. R2 is used only to limit the current through D1 in the case of D1 starts conducting.

You still need R1, Q2 and R3 to drive the P-MOSFET.

Btw, the voltage at junction of R3 and R2 doesn't have to go down to 0V. It is sufficient that the voltage at the P-MOSFET's gate relative to the P-MOSFET's source is negative enough in order to make the P-MOSFET turn on properly. The ball park estimate is that the gate voltage relative to the source voltage needs to be around 2*Vgsth. For example, if the Vgsth = -3V, the minimum voltage at junction of R3 and R2 should be about 12V - 2*|-3V| = +6V in order to make the P-MOSFET conducting and make the relay turn on.

I also mentioned a PNP in TO220 (see my circuit suggestion #3 above). This was just a very crude estimate as it would allow currents up to 1A. As your maximum current is approx. 200mA, a cheap 2N2907 should do. 2N2907 is also available in TO-18 metal can for better thermal handling should the transistor get too warm. If the base current is 10mA ... 15mA, the 2N2907 should saturate well enough with -200mA collector current, thus the dissipation is approx. 0.2mA * 0.5V ~ 100mW.

[mikerj]

Can you possibly elaborate on this? I understand I selected N-ch when I wanted P-ch, but I don't really understand why. I get that I'm "above" the load, but I thought that the circuit would "see" an activated N-ch as an open circuit and happily flow through.

The issue with a P-ch is I'm not going to readily be able to control the voltage going to my micro. It's going to be a -12-14V or so because that's what I'm feeding in on the source, yea? As where N-ch is a lot easier to deal with.

The point is that for an N channel, the gate needs to be at a positive voltage with respect to the source pin.  This makes things very easy for low side switching since you tie the source pin to ground, and your micro supplies it's 3.3v output to the gate which is enough to turn on a logic level MOSFET.

If you want to use an N channel on the high side of your load, you still have to raise the gate voltage above the source voltage.  The source voltage in this case will be your supply voltage (12v), so your micro has to apply the supply voltage plus whatever the required Vgs is to turn the MOSFET on, if it's 3.3v then you need to apply 15.3v to the gate pin.  Obviously this adds a lot of extra complexity since you now need to generate this high voltage.

With a P channel, the source is still at your supply voltage (12v) but now you need to apply a voltage to the gate which is negative with respect to the source.  This is easy, since 0v is negative with respect to 12v.  However, then you have the problem of switching the MOSFET off, since you now need to apply 12v to the gate pin to achieve this, and obviously your micro can't do this (unless it has a high voltage open collector output pin).  In this case you need a second transistor to use a voltage translator.  Another thing to note is that you must not exceed the maximum permitted gate-source voltage of the MOSFET, which can be quite low.  You can use a potential divider or a zener circuit to limit the voltage if this is a problem.

[dom0]

Ok, so, I took Kalvin's two normally open and IanM's minimal parts designs and put them in sim. They all seem to work well, but I have a bit of confusion maybe someone could help me clear up?

In IanM's design, I'm seeing a LOT of current being sunk at my GPIO pin. Far too much really. For this project I will want to make my micro sleep and wanted the entire board to be under 1mA quiescent. So if I want to leave my interrupting transistor circuit "on" so that if the user presses the switch everything still works, I can't be wasting a lot of power on the BJT and the mosfet. There is maybe only one or two circuits I'd do this "constant" activation with, the rest can wait until I wake the circuit which means there is an infinite energy source plugged in.

Here is what I drew up for IanM's design (please excuse the terrible appearance):
[]http://oi60.tinypic.com/wjzw41.jpg[/]  It's saying approx 124mA being sunk at the GPIO which is way beyond acceptable. Granted, I kind of used a generic MOSFET because my sim program doesn't have a huge library.

That's cause a PNP common-base circuit is not really suitable for switching DC. Change that stage to NPN common-emitter as I've shown above and the GPIO current will be <<1 mA.

[jnz]

That's cause a PNP common-base circuit is not really suitable for switching DC. Change that stage to NPN common-emitter as I've shown above and the GPIO current will be <<1 mA.

The NPN pulling the PNP for the sigh side is a really common circuit. Is the only advantage over what you posted that it allows a close to 12V output from the PNP's emitter? Switching speed seems ok, because both NPNs get fairly positive voltage and ground when needed.

I ran the circuit you posted in spice-ish.
http://s7.postimg.org/cp8ikmujv/dom0_dual_NPN_low_Q.png
Seems good. It's normally closed which has pros and cons for me, I'll have to balance that out. Seems to be .256mA when the GPIO is putting 3.3V out which opens the relay circuit, and effectively no current when the GPIO is 0V which closes the circuit again. Great! But there is quite a bit 12mA of loss from 1K down to first collector when I want the relay to be off..... When I adjust that 1K to be higher to prevent loss, I'm also reducing the voltage to the relay (going to 10K gives me better loss, but only 5V at the relay). So I'm thinking I see the issues with this now.

If I can get Kalvin's 3rd example with the NPN/PNP (which I've found other examples of online) to run off of higher resistances I feel like I can balance that out well with loss at the micro and overall. At least that's the current idea. The parts count is relatively low but I'm not sure if I can find parts in the right pacakges with the rain gain, etc.

Maybe I'm way off with the issues of NPN/NPN vs NPN/PNP?