What type of antialiasing filter is used in a digital scope?

[MentalFloss]

I am considering what filter to use as an antialiasing filter for a low-budget digital scope but the most obvious candidate a Bessel filter, giving constant group delay, just can't achieve the roll off required to adequately suppress frequencies above the Nyquist frequency. So what do oscilloscope manufacturers use? The particular design I am considering would be 150MSPS ADC and about 30 MHz analog bandwidth.

[MentalFloss]

Thanks mojo-chan. I'm new to the forum and can't seem to locate the Rigol thread  - do you have a link please? Any chance also of a link to a datasheet for a typical programmable filter used in this type of application?

[Galaxyrise]

mojo-chan may be referring to https://www.eevblog.com/forum/testgear/first-impressions-and-review-of-the-rigol-ds2072-ds2000-series-dso/
It's a bit of a long read, though

Stochastic sampling, aka random decimation, is the Agilent-patented means of Anti-aliasing.  That may help narrow your search.  In general, it's best to search the site with Google rather than using the forum's own search.  Something like stochastic site:eevblog.com can help you find https://www.eevblog.com/forum/testgear/first-impressions-and-review-of-the-rigol-ds2072-ds2000-series-dso/1510

[Marco]

Stochastic sampling, aka random decimation, is the Agilent-patented means of Anti-aliasing.

That's an algorithm they use for display as far as I can see, also the patent seems to have run out.

[Galaxyrise]

That's an algorithm they use for display as far as I can see, also the patent seems to have run out.

That Rigol's affects display and not capture is why it was being discussed so much in that thread

[T3sl4co1l]

Why filter useful bandwidth?  I bet the ADC goes beyond 800MHz analog bandwidth.

Do you have a very imprecise trigger circuit, or no trigger at all and must sample real time instead?

I wouldn't be surprised if most scopes do digital postprocessing and always sample at full rate.  Variable/switched bandwidth preamps and such do exist, so maybe some are doing it that way too.  Maybe even both, for the cleanest filtering (though a sharp filter response is rarely required, or even very desirable, for a scope).

Tim

[MentalFloss]

Why filter useful bandwidth?  I bet the ADC goes beyond 800MHz analog bandwidth.

You have to filter in the analog domain to prevent (or at least minimise) aliasing.

[CaptnYellowShirt]

(I have a feeling I'm about to be shot here but, what the hey...)

You may not even need an AA filter. This is only important if you're trying to interpolate your results (e.g. sinc function) or view what you're sampling via some spectrical decomposition (FFT, Z-domain).

And even if you need those things, do you expect to be measuring a lot of power beyond 1/2 the max sample rate?

[tonyarkles]

(I have a feeling I'm about to be shot here but, what the hey...)

You may not even need an AA filter. This is only important if you're trying to interpolate your results (e.g. sinc function) or view what you're sampling via some spectrical decomposition (FFT, Z-domain).

Not shot, but gently corrected. A scope without an AA filter is going to lie to you. Since the OP is talking about a low-budget scope, they're probably not looking at a super high speed ADC. Let's say they've chosen a 50MSPS one. Without the front-end AA filter, a 49MHz signal is totally indistinguishable from a 1MHz signal - they'll both show up exactly the same on the display. It's much better to have no signal appear (because it is too high frequency) on your scope than to have a deceptive one show up.

[CaptnYellowShirt]

Yup. You're right. I tend to think of those things in the freq domain. But the sample points will be exactly the same. Your mind does the interpolation in the end, whether you want it to or not.

[MentalFloss]

I found a programmable filter as mojo-chan suggested here: http://www.analog.com/en/rfif-components/rfif-attentuators-vga-filters/adrf6510/products/product.html#product-documentation

The problem is it doesn't go down to DC which is essential for an oscilloscope. Can anyone link me to a programmable filter that would be better suited for this application please?

[KJDS]

I'll have a crack at a design of an LC lowpass tonight. There's bugger all on tv and the gf is working a nightshift.

An idea of a spec will help.

[T3sl4co1l]

Blindly claiming that an unfiltered scope will "lie" fundamentally misunderstands: 1. the phenomenon of antialiasing, 2. the sampling reconstruction theorem, 3. oscilloscope functionality, and 4. ignores if not outright denies the option of equivalent time sampling.

The sampling window jitter limits how fine an equivalent sample rate you can achieve; this is usually in the single digit ps, so you can push 10s, even 100s of GSa resolution on repetitive signals.

How much do you pay for a 150MSa ADC?  Not a few bucks I'm guessing.  Seems like a damn shame to throw away that 500MHz bandwidth (or whatever it is).  After the front end and all, you're probably not going to want to actually shoot for that, but even an order of magnitude difference is easily achieved (i.e., 200-300MHz instead of 30).  Wouldn't it make sense that your front end, and your timing generator, are equally high performance (costly) as your ADC?

Tim

[MentalFloss]

I'll have a crack at a design of an LC lowpass tonight. There's bugger all on tv and the gf is working a nightshift.

An idea of a spec will help.

Well I can get a 150MSPS ADC for about £20 and I reckoned that a discrete component filter (again for about £20 in components) might be able to give me (near enough) flat to 30MHz and a roll off to at least 60dB attenuation at the Nyquist frequency (75MHz). Input and output impedances should probably be low (50 ohms) otherwise the capacitor values get stupidly low. The limitations of a discrete design seemed to mandate those sort of figures but if there's another low-budget way to do things I'm all ears.

I've got a free design program that can do this with a 10 pole Butterworth but, of course, that's a compromise because there's some ringing on the step response (it's not too bad and would be a good cost/performance compromise if there's nothing better). I thought a Bessel filter was ideal because it has near enough constant group delay but the stop band attenuation is naff. Anyway I'd be interested in anything you can come up with.

[marshallh]

Blindly claiming that an unfiltered scope will "lie" fundamentally misunderstands: 1. the phenomenon of antialiasing, 2. the sampling reconstruction theorem, 3. oscilloscope functionality, and 4. ignores if not outright denies the option of equivalent time sampling.

The sampling window jitter limits how fine an equivalent sample rate you can achieve; this is usually in the single digit ps, so you can push 10s, even 100s of GSa resolution on repetitive signals.

How much do you pay for a 150MSa ADC?  Not a few bucks I'm guessing.  Seems like a damn shame to throw away that 500MHz bandwidth (or whatever it is).  After the front end and all, you're probably not going to want to actually shoot for that, but even an order of magnitude difference is easily achieved (i.e., 200-300MHz instead of 30).  Wouldn't it make sense that your front end, and your timing generator, are equally high performance (costly) as your ADC?

Tim

This is correct, TI/national and AD both have appnotes describing the impact of sample clock jitter on the ENOB and SFDR of the adc. For an 8bit adc you can lose several dB by using an uncleaned crystal oscillator (which may have anywhere from +-50-400ppm stability) or less with a MEMS based oscillator (typically 5-20ppm). This is why you can't just use an FPGA pll output, because those have 400-600ppm uncertainty... Only suitable for digital.
And it gets harder once you need more than 8 bits.
If you want ETS on your 100msps converter, consider using a CPLD with fixed propagation delays to create phase offsets. It's how the various chinese mfgs did it..

[MentalFloss]

After the front end and all, you're probably not going to want to actually shoot for that, but even an order of magnitude difference is easily achieved (i.e., 200-300MHz instead of 30).  Wouldn't it make sense that your front end, and your timing generator, are equally high performance (costly) as your ADC?

I understand the effect of clock jitter but could you explain how I would get 300MHz bandwidth from a 150MSPS ADC (if that's what you're saying)?

[KJDS]

A seven section bessel with some added elements to add some finite frequency transmission zeros looks like the attached. Only 50dB stopband, should probably be taken to 9 or 10 elements if you really want more rejection.

[nctnico]

After the front end and all, you're probably not going to want to actually shoot for that, but even an order of magnitude difference is easily achieved (i.e., 200-300MHz instead of 30).  Wouldn't it make sense that your front end, and your timing generator, are equally high performance (costly) as your ADC?

I understand the effect of clock jitter but could you explain how I would get 300MHz bandwidth from a 150MSPS ADC (if that's what you're saying)?

You can use equivalent time sampling. You'd need a steady trigger for that. Like marshallh already mentioned: jitter is your biggest enemy. In my onw USB oscilloscope design I ended up needing better than 3ps jitter to get 10bits from a 100MS/s ADC. For that you'll need a dedicated clock chip. But before you embark on the electronics side of this project think about what your user interface is going to look like. Building the hardware for an oscilloscope is peanuts compared to the user interface software.

[MentalFloss]

A seven section bessel with some added elements to add some finite frequency transmission zeros looks like the attached. Only 50dB stopband, should probably be taken to 9 or 10 elements if you really want more rejection.

Thanks KJDS. Yes that's not too shabby at all. I simulated the step response and it is bessel with a bit of well damped ringing. Can I ask what you used to design this please as the freebie filter design software I use doesn't allow for the 'extra' tweaks that you have?

Oh, the downside is the 7pF capacitor. I think this is pretty low and will require good PCB design to avoid parasitics affecting it. Is there a way to design this for a minimum 20-30pf capacitor?

[MentalFloss]

You can use equivalent time sampling. You'd need a steady trigger for that. Like marshallh already mentioned: jitter is your biggest enemy. In my onw USB oscilloscope design I ended up needing better than 3ps jitter to get 10bits from a 100MS/s ADC. For that you'll need a dedicated clock chip. But before you embark on the electronics side of this project think about what your user interface is going to look like. Building the hardware for an oscilloscope is peanuts compared to the user interface software.

Right I see how that works but of course it has the major downside of needing repetitive waveforms to work properly so it only has use in those situations. A useful technique where it works though.

I have thought about the user interface, in a general way, at this point. I have been out of electronics for twenty years and have forgotten most of what I knew so this is my project to get back into it. I intend to have an active probe sending display samples to a smartphone through bluetooth. Not having to build the display keeps it low-budget. I'm currently teaching myself java and all sorts of stuff.

If you have any info on the programmable filters mentioned earlier in the thread I'd like to hear about it.

[KJDS]

I took the g-values from the link below. For a cheby i have a spreadsheet that calculates these but haven't done that for a Bessel

http://www.rfcafe.com/references/electrical/bessel-proto-values.htm

I stuck the g-values into a spreadsheet that I wrote ages ago which gives me the values of the series L and shunt C. I set the cut-off freq as 50MHz. Then I added the extra Cs in parallel with the series Ls and put one extra shunt inductance in. The whole lot was simulated using RFsim99. The extra components were added in one at a time and tweaked to where I wanted the extra attenuation.

[CaptnYellowShirt]

The program 'qucs' has a nice filter synthesis feature. The program on the whole has really grown on me. It's my first choice for a quick, easy, and powerful circuit simulation tool.

[MentalFloss]

KJDS if you're still around can you explain the design process for a 10th order bessel please as I think that would do the job perfectly. I can get the element values from that link you gave to make a standard bessel filter but what knowledge do I need to be able to calculate the added components like you did? Thanks.

[KJDS]

KJDS if you're still around can you explain the design process for a 10th order bessel please as I think that would do the job perfectly. I can get the element values from that link you gave to make a standard bessel filter but what knowledge do I need to be able to calculate the added components like you did? Thanks.

Get RFSim or another suitable linear simulator working. Get the standard Bessel filter working with a cutoff freq of 50MHz. Then add a C in parallel with the largest series inductor. Choose a value to give resonance at about 75MHz. Analyze the response and you'll see a dip in the through response at 75MHz.

Next add a capacitor in parallel with the next largest inductor. I'd guess that aiming a resonance at 85MHz will give something reasonable. Then repeat with all the other series inductors so that the humps in the stopband are at the required level.

You may find that you still need some more rejection at higher frequencies. If so then use small inductances in series with the shunt caps. If they are less than 10n then realize these as printed, so just a suitable length of track on the board.

Once you've got a suitable response then the real work starts.



Find inductors of about the right value and with a self resonance well above 100MHz. Work out the ESR of each and include it in the model. If teh passband loss is too high, choose a more expensive inductor.

Work out what the internal capacitance of the inductors is from their specified self resonant frequency. Deduct that from the capacitor value you used in the simulation to get the value you need on the circuit board. Build it, curse a little, drink some tea and play with the capacitor values until you achieve something close to the desired response.

[MentalFloss]

Thanks KJDS. Looks like I've got my work cut out but it'll pass some cold wintery nights! 

I assume you choose 50MHz because that guarantees a flat response to 30MHz?

And is there any standard way to increase the values of the smallest capacitors - I'd rather avoid having most of the capacitance made up from board parasitics.