I see there is a little debate regarding the output impedance. Never measured it IRL in fact, that's what I saw in the datasheets. I'd be interested as well to see the actual measurements, if someone does this. I'm away from my lab for a few months (hence my extra time for simulations) and apart from generic, slower and older CMOS/TTL inverters I don't have comparable parts yet.
Going back to my main subject, I'd like to have your opinion on my simulation model.
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I redrew the concept of my behavioral model of the switch on KiCad so it looks less messy. I took the NX3DV221 switch as a reference, which claims to have a maximum 6
ON resistance and a parasitic capacitance of around 5-6 pF parasitic capacitance which actually varies between the state. It is not as accurate as an actual model, but it can allow me to have a rough idea of the part's flaws. Is this circuit not too far from the reality ? I used this Analog Device's application note:
https://www.analog.com/media/en/training-seminars/tutorials/MT-088.pdf to be sure about the parasitic elements but it's only about SPST switches.
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This is a simplified schematic of how I wired the switch, where it should switch between the adjustable voltage and 0V. The actual simulation schematic is attached for information. The 2 ports subcircuit is the transistor voltage regulator circuit I borrowed from PCB.Wiz. Don't pay too much attention to the filtering cap; I just slapped it without calculation, but I know a combination of capacitors will be needed so the ripple is kept low enough on both high and low frequencies. It gave somewhat acceptable results on the simulation anyway.
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And finally, here are the simulation results. It looks decent but has some little quirks. As you can see the risetime is pretty fast so it seems to perform well, but the falltime is longer, just as if parasitic capacitance take longer time to discharge. It's still within my specifications (~ 2 ns) but I wonder if something's wrong with my model.
Edit: damnit, how do you add pictures?