Use an ultralow quiescent current OPAMP as a buffer for the potential divider and increase the divider resistors by an order of magnitude and you should be able to get that down to under 2uA, maybe even under 1uA. The fly in the ointment is its then far more sensitive to surface leakage - you may need to slot the PCB under the resistors and even put a guard ring driven by the OPAMP output round its input node.
The other approach is to disconnect the top end of the divider when not sampling, and sample infrequently enough that the divider current is negligible. Typically this is done with a small signal P-MOSFET, which requires level shifted drive, most conveniently provided by a N-MOSFET, using a complimentary dual pair to get them in the same package. Add two resistors for P gate pullup and N gate pulldown, and your BOM is only four resistors + one dual MOSFET (+ an extra I/O pin).