At one time National made a FET input comparator, the LF311. It looks like it was phased out in the 90's. I built a frequency counter in the 70's using one of these things. Even back then it wasn't particularly fast with a response time of 200 ns. This implies a 5 - 10 MHz frequency limit which was just good enough for the rest of the counter.
The LF311 is about the only one I know of and I suspect it was discontinued because it was just a dumb idea. Tektronix used custom hybrids for their logic analyzers which included a JFET buffer followed by an ECL line receiver.
The major problem is capacitive coupling between the output and inputs and between the inputs. In an operational amplifier, a small amount of feedback capacitance can be added to neutralized the pole formed by the input resistance and capacitance at the inverting input but comparators are not compensated so that will not work for them. It also will not work for a current feedback amplifier without some additional cleverness.
Coupling from the output to the inputs and between the inputs when the source impedances are high can cause all kinds of weirdness. And if you use low source impedances to prevent this, then a high impedance input is no longer required. The corner cases left over where a low input bias current is desirable were just not enough.
Of course CMOS input comparators have all of the same problems and the same solutions; drive them with low source impedances.
I think David Hess knows of what he speaks. A frequency counter with a good input circuit is a pleasure to use because it isn't fooled by abberations in the input signat. I preferred Tek scopes over hp's because, to me anyway, they had better and more consistant triggering. Since you can't see the trigger points with a frequency counter, how do you know it's the right frequency?
Tektronix's earliest counters used oscilloscope input circuits and they worked great, better than most later counters. The 7D15 shown below is a completely discrete design and includes compensated input attenuators and an HF gain trim. Notice how the trigger level is added to the input signal and only the last stage (1) adds hysteresis and operates with a fixed trigger level; this is effectively a schmitt trigger with one input and one output so no comparator is used even to support a variable trigger level. A tunnel diode based circuit would work this way and support incredibly high speeds.
If I was going to duplicate a good but simple design, I would consider the HP 5314/15/16 which uses a JFET buffer to directly drive an AMD (!) AM687 comparator. The comparator then drives a differential pair to create an ECL logic output. (2) These counters support a mode where the level control becomes a sensitivity control and the designer abused the latch enable input of the AM687 to provide this so finding a suitable modern comparator to act this way might be a problem. Replace the JFET with your favorite high bandwidth JFET or CMOS operational amplifier operating as a voltage follower unless you need higher performance.
(1) There are two last stages in parallel. One of the two is enabled so triggering on the rising or falling edge is selected instead of trying to invert the analog signal at an earlier point. A modern design could just stick an exclusive-or gate after the comparator to select which edge to use.
(2) See the application note I mentioned which discusses comparator level shifters to drive different types of logic.
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