Unused inputs on TTL (74LS) and CMOS (74HC) chips

[ElectroSone]

I'm currently doing some early beginner breadboard projects using either 74LS or 74HC chips (no, I don't mix them).

I'm aware of the recommendation to not leave unused inputs on these chips unconnected, and instead tie them high or low. I'm also aware there's recurring questions about this. However, older threads on this topic can get quite chaotic, with a variety of different opinions of an anecdotal nature or mixing of factoids about TTL and CMOS.

All of this still leaves me a bit confused sometimes, and I think the more seasoned folk here have a great opportunity to make this the one thread people will find in their searches, and get their answers from!

Here's a few things I've read before:

• It's OK to tie inputs directly to Vcc/ground vs. There should always be a resistor used
• Use a 10k resistor vs. Use a 1k resistor
• Depending on the chip type, tying to Vcc or ground will use less power

I'd love for some of you in the know to provide a definitive summary here, perhaps in the form of rules or a table.

(a) Is it OK to tie directly to Vcc/ground, or is a resistor the way to go? Does this differ by TTL and CMOS? Does it differ by older chip manufacturing standards vs. modern incarnations? What's the correct way to identify it in a data sheet?

(b) What's a good general value resistor to use, if a resistor is used? What are the exceptions and why? Is there a difference between TTL and CMOS here?

(c) Regarding whether to tie to Vcc or ground to keep power use to a minimum, what are good rules of thumb to follow?

I imagine there's a "If you got no time to think, do X by default" here, and then a "this is what's really going on and why".

Links to resources appreciated, too!

[RoGeorge]

It depends.  Best answers are in the datasheets and/or in the application notes specific to each family.  For example, search for the word "unused" inside this databook:
http://www.bitsavers.org/components/ti/_dataBooks/1981_TI_The_TTL_Data_Book_For_Design_Engineers_2ed.pdf

[retiredfeline]

You missed another alternative, tie it to another input in the case of N/{AND,OR} gates. But not N/XOR gates.

Personally I don't think it matters whether you tie (pull up for LS) it via a resistor or not. In the case of HC you should tie it to something. For LS you might get away with no connect and tying high might reduce current a bit, but you don't alwaya hsve the choice and I think it's unimportant in the scheme of things. If current is a consideration you should be using CMOS families.

[Siwastaja]

You can still get TTL parts in 2022? I haven't checked, because those have not been used in new design for... what, maybe 40 years?

Are you sure you want to spend any time learning this TTL thing? After all, it's totally and fundamentally different. Not difficult of course, but a beast of its own. Do note that in 99.999% cases, when people spout out the magical "TTL" word in 2022, they don't mean TTL at all, but something else. (Like "USB-TTL adapter" where "TTL" means 5V or 3.3V CMOS. Go figure.)

So unless you plan to do some repair/restoration of antique designs, you will be using CMOS parts anyway. Note there are CMOS parts with TTL-compatible input levels, namely 74HCT series, but this only affects the input threshold levels; otherwise, it's CMOS.

With CMOS parts, this is all simple: it's a good idea to supply either GND or Vcc to the inputs. Direct connection to GND is fine. Direct connection to Vcc is fine given that it's the same Vcc part is powered from. Pull-down to GND is fine. Pull-up to Vcc is fine. Pull-up resistor can be large, even a Megaohm is fine (given good layout, not to pick up noise). Don't leave the inputs floating. It's not disastrous, but may increase power consumption or with very bad luck, create some oscillator thing with parasitics and external noise.

[T3sl4co1l]

CMOS: tie wherever is convenient and logically correct.  Resistance doesn't matter, of course larger values will be more sensitive to noise.

TTL: pullup with resistor.  The input structure can latch like an SCR if overdriven, apparently this is a risk if hard tied to +V.  I forget how... is it in relation to multiple inputs, overdriving one with the other tied with +V?  Anyway, something like that.

TTL can be left open (inputs pull high by default), but are then sensitive to noise.  A pullup is recommended.  Open CMOS inputs will drift around and are even more sensitive to noise so must be tied somewhere.

Tim

[Ian.M]

Yes, those were the rules of thumb I was taught way back in the day.  74xx bipolar TTL with an S in the part number *should* have an input structure resistant to such latch-up, but why risk it?  A 1K pullup, possibly shared between multiple nearby inputs was regarded as industry best practice when you needed a fixed logic 1 for TTL.

[bostonman]

I know the power consumption is negligible, but, if unused gates exist, which method uses less power (tying high or low)?

[Ian.M]

For least power, its generally bipolar TTL: tie high as the inputs source about half a mA current if pulled low, and CMOS: don't care as long as its pulled to
a valid level, not left floating.

[edavid]

TTL: pullup with resistor.  The input structure can latch like an SCR if overdriven, apparently this is a risk if hard tied to +V.  I forget how... is it in relation to multiple inputs, overdriving one with the other tied with +V?  Anyway, something like that.

It's not a latchup issue.  Original TTL inputs are NPN transistor emitters.  If you apply a voltage that's too high, the emitter base junction will break down.  As we know, this degrades the transistor beta and other characteristics.  (In this case it's a low beta gold doped transistor, but still.)

Looking at the datasheet, max V_CC is 7V, max input voltage is 5.5V.  So if you have emitter inputs tied to V_CC and your power supply rises above 5.5V, those inputs may break down.  There is also a 5.5V max interemitter voltage spec.

The diode inputs used in 74LS (and 74S, 74F, etc.) have a higher breakdown voltage, so this is a non-issue.  The datasheet shows max V_CC of 7V and max input 7V.

OP says he is only using 74LS, so he can feel free to tie inputs to V_CC.  Even if he did use standard TTL, I think he could make sure his breadboard supply voltage didn't rise above 5.5V, so again it wouldn't apply.  OP, don't worry about it.

[edavid]

For least power, its generally bipolar TTL: tie high as the inputs source about half a mA current if pulled low

But that's only the power due to the input.  Depending on the IC,  the internal circuit may draw significantly less power if the input is tied low.  This is probably something you would need to test if you cared.

[Siwastaja]

But that's only the power due to the input.  Depending on the IC,  the internal circuit may draw significantly less power if the input is tied low.  This is probably something you would need to test if you cared.

Well, that's functionally obvious if it's some kind of "chip enable" signal.

For simple logic gates, the static consumption in both states is very closely the same, in CMOS.

[edavid]

But that's only the power due to the input.  Depending on the IC,  the internal circuit may draw significantly less power if the input is tied low.  This is probably something you would need to test if you cared.

Well, that's functionally obvious if it's some kind of "chip enable" signal.

For simple logic gates, the static consumption in both states is very closely the same, in CMOS.

Yes, my comment only applies to TTL.

[DavidAlfa]

They must set to a stable position just for avoiding random oscillation, just like op-amps.
On the cheap: Just connect unused inputs to ground, leave outputs unconnected.

[Siwastaja]

On the cheap: Just connect unused inputs to ground, leave outputs unconnected.

This is nowadays so obvious, and easy from the PCB layout perspective, you already have a ground plane, and connecting unused pins to it only makes the ground plane better.

Back in the days of TTL, things were worse; grounded unused inputs consumed extra current, so they had to be tied to Vcc instead, and worse, often through a resistor (although some families allowed direct connection). Extra parts and more challenging PCB routing.

[T3sl4co1l]

TTL: pullup with resistor.  The input structure can latch like an SCR if overdriven, apparently this is a risk if hard tied to +V.  I forget how... is it in relation to multiple inputs, overdriving one with the other tied with +V?  Anyway, something like that.

It's not a latchup issue.  Original TTL inputs are NPN transistor emitters.  If you apply a voltage that's too high, the emitter base junction will break down.  As we know, this degrades the transistor beta and other characteristics.  (In this case it's a low beta gold doped transistor, but still.)

Looking at the datasheet, max V_CC is 7V, max input voltage is 5.5V.  So if you have emitter inputs tied to V_CC and your power supply rises above 5.5V, those inputs may break down.  There is also a 5.5V max interemitter voltage spec.

Ah, that makes more sense, thanks.

(Well, I suppose it could still cause latchup, because BJT breakdown is weird -- but that's an edge case and a side effect of breakdown in the first place.)

Tim