LDO Controller - simulation of a devkit schematic

[Scott_H]

Hi there,

I'm rolling my own MPU carrier board, and kinda fell down a rabbit hole. A schematic in the user guide for a somewhat similar board https://www.microchip.com/content/dam/mchp/documents/MPU32/ProductDocuments/UserGuides/SAMA7G54-EK-User%27s-Guide-DS50003273.pdf (Page 74, schematic pg8) uses a P-fet controlled by an LDO output from a KSZ9131RNX to supply a constant 1.2v back to the KSZ9131RNX from a 3.3v rail.

I'm trying to simulate it in LTspice before I build the thing, at least in part because I don't completely understand how it operates. I've attached a LTspice .asc file I made to check it wasn't some analog magic and a screenshot of the userguide schematic section.

My thinking is that the LDO controller must be sensing the 1.2v rail fed back into the KSZ9131RNX, and raises/lowers the gate voltage to the p-fet to suit, but I would like a sanity check in case there's something obvious I'm missing. (very possible, this is not my comfort zone)

Thanks for any pointers!

[ataradov]

I can't check the LTSpice stuff, but you are correct. LDO controller adjusts the gate voltage until AVDDL is 1.2 V.

If you look at any LDO design, you will see the same transistor. In this case this transistor is external and the rest of  circuit is inside  the PHY.

This is a really strange design, but I guess they had their reasons to do it that way.

[langwadt]

I can't check the LTSpice stuff, but you are correct. LDO controller adjusts the gate voltage until AVDDL is 1.2 V.

If you look at any LDO design, you will see the same transistor. In this case this transistor is external and the rest of  circuit is inside  the PHY.

This is a really strange design, but I guess they had their reasons to do it that way.

it is in the datasheet the the pin it a control output to control a p-fet to generate 1.2V

it is probably done that way to save some chip area and not least to get some power dissipation off the chip

[ataradov]

it is probably done that way to save some chip area and not least to get some power dissipation off the chip

That would be my guess too, especially for the power part.

They don't seem to specify the current consumption on the 1.2V pins. They specify that transistor must be able to handle 500 mA. I'm not sure how you are supposed to select external regulator if you want to go that way.

[langwadt]

it is probably done that way to save some chip area and not least to get some power dissipation off the chip

That would be my guess too, especially for the power part.

They don't seem to specify the current consumption on the 1.2V pins. They specify that transistor must be able to handle 500 mA. I'm not sure how you are supposed to select external regulator if you want to go that way.

https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/00002841D.pdf

table 6.4,  ~220mA typical with 1000BT traffic

[ataradov]

table 6.4,  ~220mA typical with 1000BT traffic

Typical Microchip issue. If you just google search for the device and go from the first link, it will give you a link to the rev B of the datasheet where this information is missing.

Happens all the time for MCUs too.

[SiliconWizard]

Yes, they have just integrated the controller part of the LDO but left the pass transistor as an external component.
The simulation you tried is not correct as you have just fed 1.2V to the PMOS's gate, which will turn it fully on in this case and so will output 3.3V. The chip integrates a controller with feedback indeed.

That has the benefit of only requiring an external PMOS rather than a full-blown LDO (cheaper) while not having to integrate a high-dissipation power transistor inside the chip itself, which would be unconvenient as it has to dissipate as much as 1/2W, which is a lot.

Note that you can absolutely use a separate external LDO instead if you so prefer (in particular, using a switching converter instead would save significant power), as the DS states.

LDO Controller
 LDO_O
 AO
 On-chip 1.2V LDO controller output.
Output
This pin drives the input gate of a P-channel MOSFET to gen-
erate 1.2V for the chip’s core voltages.
Note:
 If the system provides 1.2V, this pin is not used and
can be left unconnected.

[langwadt]

table 6.4,  ~220mA typical with 1000BT traffic

Typical Microchip issue. If you just google search for the device and go from the first link, it will give you a link to the rev B of the datasheet where this information is missing.

Happens all the time for MCUs too.

annoying,

my first google hit is: https://www.microchip.com/en-us/product/ksz9131 which has links to 00002840C.pdf and 00002841D.pdf both with the table of currents

second google hit is directly to the older 00002841B.pdf without table

[PCB.Wiz]

I'm trying to simulate it in LTspice before I build the thing, at least in part because I don't completely understand how it operates.
I've attached a LTspice .asc file I made to check it wasn't some analog magic and a screenshot of the userguide schematic section.

How does that check for 'analog magic' ?

My thinking is that the LDO controller must be sensing the 1.2v rail fed back into the KSZ9131RNX, and raises/lowers the gate voltage to the p-fet to suit, but I would like a sanity check in case there's something obvious I'm missing. (very possible, this is not my comfort zone)

Yes, there is 'analog magic' inside the LDO drive pin, it needs to do exactly what you say.
Why did your sim circuit not match what you wrote ?

They give you the parts and values, and even calculate the power dissipation, so you can just buy the parts and build it.

Note they mention 525mW, which will need decent copper areas allocated to the SO-8 power FET.

[Scott_H]

Why did your sim circuit not match what you wrote ?

They give you the parts and values, and even calculate the power dissipation, so you can just buy the parts and build it.

The sim circuit matched the schematic provided - adding more items would be me simulating my imagination instead of what I was being asked to replicate.

I don't like just buying parts and building, I prefer having some idea of why I'm connecting things - this way, I get to have conversations like we're having now.

Thank you for confirming I was on the right track, and thanks everyone for posting. Learnt a bit!

[magic]

Simulating this is impossible/pointless without having a model of what's inside the chip. Just connect some P-ch FET (maybe the same which was used on that other board) and pray that it works and doesn't oscillate.

An advantage of using the built-in LDO instead of external one is that you don't need to worry about voltage drops on PCB tracks and internal chip connections - the rail will be sensed and regulated as it appears inside the chip.