Ultra precise Linearity test of the SD ADC.

[MasterT]

1.
 Voltage divider, 've seen a few topics on this forum discussing measurements of linearity using this approach.  Idea is simple, measure voltage between A-B and B-C and sum up. Total must be A-C (Reference Voltage). See picture "Simple divider".
(B-A + C-B) = A-C
If not, we have linearity error at the middle.
Issue: to have good accuracy (very) many measurements should be done to average
results and get SNR level under control below 1 ppm. Manually to do this work is a nonsense,
to put arduino on duty - have to buy relays. One point in the middle of scale obviously is not
enough, though a lot of relays. More issues: price, reliability, complexity of assembling etc.





2.
 Propose.
It would be nice to have a DAC, 8 - 12 bits in place of voltage divider. Unfortunately,
I've never seen a DAC with two outputs from the same string.
But there are dual DAC's freely available. Look at the picture: it's the same as initial gear
only with two ladders.


Middle points B & B' have different potential, but since arduino is
doing measurements, I don't care - just One more measurement between B and B' and all
math from paragraph 1 is Correct !
 (B-A' + C-B' + B-B') = A-C'
 As voltage difference in between B-B' is small. non-linearity is negligible and not counted. For example,
 chart MCP3551-60 INL. Differential inputs, claimed value < 6 ppm. Look at the middle for low voltages, line crosses zero symmetrically.

 
3.
Results.
So far I observed a lower level INL of mcp3551-60, below 1 ppm, but not sure if my software is bug free - there are huge noise reduction processing involved.  Fastest 3 points scan (2.048 V steps) tooks 3x32 = 96 seconds. Small scales steps ( < 0.25V ) consumed a lot of time, since idea is worked only all ladder scanned from the ground to the reference. Temp stability requirements for DAC is tough.
 Would update later on if I have more results to share.

[MasterT]

I think, 'd add results I have this morning. It helps me to explain "state machine" of my approach.
In the image you 'd see the blocks of 4 measurements, settings of the DAC-1 & 2, and voltage that lags  one line.
So, first line DAC-1 in the middle (2048), DAC-2 close to ground (4) and voltage taken -2.047533.
Next "state" DAC1 & 2 at 2048 and voltage -0.003015 ( DAC's INL not so good?).
Than DAC-1 4092 and DAC-2 2048 = -2.041114
Last step is DAC-1 4092 and DAC-2 (4) - "total", = -4.085639
As you can see, there is a difference between total and sum of 3 voltages. Diff_x (uV): -7.63
It's non-linearity at the middle of ADC,  -7.63 / 2 = -3.815 or −3.815 ÷ 4.096 = −0.931396484 ppm.

Repeating this procedure long enough, I could reduce noise down to 1 uV or so, (dif-avg: -12.32), and this gives me 0.25 ppm accuracy noise-free at this moment. Still have to do more experiments  to optimize trade of the numbers of ADC readings per each step, against short term drift of DAC's outputs

Update* - two more screenshots.

[Kleinstein]

Linearity testing is a tricky business.  An important point in using the sum of 2 voltages is that the 2 voltages to measure are independent / isolated from the ADC, so one can switch the inputs at will. This requites the test voltage part to have it's own reference independent from the ADC. Another points is that the test voltages should be relatively low impedance, so that loading them does not have much effect. If low enough in impedance the switching could be electronic as well.

Many of the ADCs have differential inputs, but the common mode suppression of these inputs is not perfect. Expect a common mode error of the same order of magnitude as the INL error. So one can not really use the differential inputs to avoid a free floating independent source part with it's own reference. So one needs two low noise reference and usually several repeated cycles to make sure one is not measuring reference drift.

[MasterT]

An important point in using the sum of 2 voltages is that the 2 voltages to measure are independent / isolated from the ADC, so one can switch the inputs at will. This requites the test voltage part to have it's own reference independent from the ADC.

Loot at the "INL Level vs Input Voltages" chart for MCP3551 ones more. I told, that INL at low voltages (at the middle), where line crosses "0" is negligible. Same apply to the maximum voltages, where INL curve crosses "0" again. I could ignore the fact, that maximum level I have actually not Vref, but one dac's "pixel" below, something like 1-4 mV lower than Vref.
Microchip make good ADC, that autocalibrates itself in no settling time, EACH cycle. So, I don't see why I need a separate reference or another meter. Think about ratiometric measurements.

Another points is that the test voltages should be relatively low impedance, so that loading them does not have much effect. If low enough in impedance the switching could be electronic as well.

DAC is buffered internally on both outputs & reference inputs sides.

Many of the ADCs have differential inputs, but the common mode suppression of these inputs is not perfect. Expect a common mode error of the same order of magnitude as the INL error.

I agree on this, its bother me, since I don't have direct 8.5 digits proof from the another meter - out of my budget.
But I tested INL shifting first step up, to 64 ( 1 / 64 of full scale ) , trying to avoid "close to ground" INL in 64 mV area, and it did show big difference. INL drops 4-6 times lower than on last screenshots.

[Kleinstein]

One could test the effect of the common mode voltage with a relatively simple test setup. Have a floating small reference of something like 100 mV or 500 mV and than use one of the DACs to to set one input to the ADC. So the ADC would measure the same test voltage with different common mode voltages.

I know that it helps to work ratio-metric with only a single voltage reference, but the simple INL test with the 2 voltages in series has the problem that one can not easy use the same reference, as this would add some common mode error. One can't have both radiometric and avoiding common mode errors from using a free floating test signal. Using 2 independent references adds some noise. Drift of the references can be converted to noise by doing multiple repeats. So often the independent reference is the lesser evil (noise) compared to the common mode problem (linearity problem).

It is not such a surprise the INL curve is anti-symmetric about 0. Many of those SD ADCs with differential input internally swap the inputs at some time to remove the offset and at the same time this also suppresses the other even powers from the INL curve. However this only applies when driving the ADC with a fixed common mode signal. When having one input fixed and only move the other around would have additional errors - e.g. some of the even powers that are no longer suppressed.

[MasterT]

Let's me rearrange my explanation, posted earlier.
1. DAC-1 in the middle (2048), DAC-2 close to ground (4) and voltage taken -2.047533.
2. DAC1 & 2 at 2048 and voltage -0.003015 ( DAC's INL not so good?).
3. DAC-1 4092 and DAC-2 2048 = -2.041114
4  DAC-1 4092 and DAC-2 (4) - "total", = -4.085639
There are 4 measurements. Two are considered INL-free (number 2 & 4) since taken at the INL = 0.
Two erroneous, this is why division by 2 in my calculation for INL
 -7.63 / 2 = -3.815 or −3.815 ÷ 4.096 = −0.931396484 ppm.

Now , common mode. If it's average both inputs (inverting and non-inverting) of the adc, than CM = 1/4  of the V-reference  for meas. #1, and CM = 3/4 for #3.  Not too close to the "rails", at least. I could only say, that  my measurements results if not exactly precise to 0.x ppm, but shows "worst case scenario" for specific ADC. It means if differential ADC has INL < 1-2 ppm with CM not centered around mid-reference, than it's very likely to have lower INL if inputs centered.

[Kleinstein]

Some (most ?) of the SD ADCs work internally pseudo differentially. So they kind of measure the voltage of both inputs and calculate the difference. If this is done the whole test with the DAC is futile, as the inputs see the same readings, just in different combinations. So one would not see the actual INL error, but mainly gets the digital zero sum. One may still get some hidden effects (like one DAC setting effecting the other). So in this case the CM error and INL error would just cancel out as they are linked to a common source (INL of the individual ADC halfs). The cancel out of the errors would not be by accident, but a systematic effect.

The DAC shown is a very low cost one, so don't expect too much (any accuracy) from it. So the 3 mV difference at 2 V is perfectly in spec and normal. Just the buffers, like other cheap OPs can have an offset of a few mV.

[David Hess]

The instrumentation delta-sigma converters that I have managed to study have chopped inputs which is consistent with high charge injection and flat flicker noise so like chopper stabilized amplifiers, should not be used with high impedance sources despite their specified input bias current and input resistance.

[MasterT]

Some (most ?) of the SD ADCs work internally pseudo differentially. So they kind of measure the voltage of both inputs and calculate the difference. If this is done the whole test with the DAC is futile, as the inputs see the same readings, just in different combinations. So one would not see the actual INL error, but mainly gets the digital zero sum. One may still get some hidden effects (like one DAC setting effecting the other). So in this case the CM error and INL error would just cancel out as they are linked to a common source (INL of the individual ADC halfs). The cancel out of the errors would not be by accident, but a systematic effect.

The DAC shown is a very low cost one, so don't expect too much (any accuracy) from it. So the 3 mV difference at 2 V is perfectly in spec and normal. Just the buffers, like other cheap OPs can have an offset of a few mV.

Topic is not to discuss DAC performance . It's about a Method or Technics to calibrate out INL of SD ADC.
Actually I intentionally used mcp4912 - to underline that technics doesn't require high precision components. Not really low TCR or stability. Settling time of the DAC is not related,  ADC is running in single conversion mode 16 msec / sample, so I put on pause for  100 usec settling time (4.5 usec required by DAC x 20 times) . ADC is halted during this period, no SPI capacitive junk flow into ADC engine, it's re-start sampling after all settle down. Re-start, as I mention , from total re-calibration offset - full scale.
And I didn't get a words out of  gibberish about accident/ cancel out / hidden effects. 

The instrumentation delta-sigma converters that I have managed to study have chopped inputs which is consistent with high charge injection and flat flicker noise so like chopper stabilized amplifiers, should not be used with high impedance sources despite their specified input bias current and input resistance.

Sorry for confusion, probably influenced by drawings I inserted above - two resistive strings. Those strings are merely to show "state machine" transit from one step of the ladder to another, up to the top reference voltage.
DAC is Buffered internally for reference inputs and outputs. Though - impedance is lower than 0.1 Ohm, I think, input of the ADC about 2 MOhm - I have about 10^-7 expected THD ground.

[Kleinstein]

The low output impedance of the DAC buffer is valid for DC. The problem with chopped / sampling inputs like the ADC is that they care about the impedance in the MHz range. This is why one sometimes sees filters with something like 100 Ohms and caps in the 1 µF range. Some data-sheets (e.g. LTC2400 as one of the early SD ADCs) extra mention that capacitance at the ADC inputs can effect the INL of the ADC. To me this is one of the hidden nasty points of AZ OPs and SD converters: you want DC precision and suddenly you should look at the impedance in the MHz range.

I understand that in the test circuit the DAC accuracy does not matter. However DAC drift can be a nuisance (requires mire measurement cycles, repeated switching through the cases) and DAC noise can be a large part of the total noise. At the low ppm level there may be even one DAC channel coupling to the other.

The common mode can effect the ADC quite a bit, and the effect is not somewhat random, but much of the errors are directly related to the voltage seen at the individual inputs, e.g. from the input switch resistance and charge injection effected by the voltage. The test with the DAC naturally has each input twice at the same level, once with a positive and once with a negative sign for the result. So at least those errors from INL and CM effect are expect to cancel out in this text. So the test is blind to those effect the CM error and INL in the described way. It looks nice to get 1 ppm for the sum of INL and CM error - but this does not exclude a large CM and INL error. The compensation would not be bad/good luck, but it can very well be a systematic effect.

[MasterT]

I understand that in the test circuit the DAC accuracy does not matter. However DAC drift can be a nuisance (requires mire measurement cycles, repeated switching through the cases) and DAC noise can be a large part of the total noise. At the low ppm level there may be even one DAC channel coupling to the other.

I do many measurements cycles, switching DAC up and down, so drift (in 3 sec interval) is not issue. Same with low frequency noise - it simple averages out. Channel to channel coupling is also not an issue, just DNL of DAC itself, like internal buffers offset, and mcp3550-60 chart shows 2ppm /volt (middle), so to have 0.1ppm accuracy  test setup could tolerate 200mV (!) of the DNL.

The common mode can effect the ADC quite a bit, and the effect is not somewhat random, but much of the errors are directly related to the voltage seen at the individual inputs, e.g. from the input switch resistance and charge injection effected by the voltage. The test with the DAC naturally has each input twice at the same level, once with a positive and once with a negative sign for the result. So at least those errors from INL and CM effect are expect to cancel out in this text. So the test is blind to those effect the CM error and INL in the described way. It looks nice to get 1 ppm for the sum of INL and CM error - but this does not exclude a large CM and INL error. The compensation would not be bad/good luck, but it can very well be a systematic effect.

I change setup to exclude CM out of equation.

Case is closed. Results:

[KT88]

A different approach might work:
A triangular waveform generated with a stable current source and an integrator.
The amplitude could exceed the input rails of the SD ADC a bit so all possible codes are tested. On the X-axis you have time which can be by orders of magnitude mor linear than the test requires. The amplitude will be propotiopnal to time - given the integrator is up to the task - which should be doable.
For the integrator part, some inspiration by mutislope ADC designs could help...
To get rid of noise, multiple runs can be averaged. Even if some codes went missing - which will happen if the test should not run forever - multiple runs will eventually fill most of the gaps.

Cheers

Andreas

[David Hess]

A different approach might work:
A triangular waveform generated with a stable current source and an integrator.
The amplitude could exceed the input rails of the SD ADC a bit so all possible codes are tested. On the X-axis you have time which can be by orders of magnitude mor linear than the test requires. The amplitude will be propotiopnal to time - given the integrator is up to the task - which should be doable.

The usual solution is to use a high purity sine source which will produce a known histogram.

[Someone]

A different approach might work:
A triangular waveform generated with a stable current source and an integrator.
The amplitude could exceed the input rails of the SD ADC a bit so all possible codes are tested. On the X-axis you have time which can be by orders of magnitude mor linear than the test requires. The amplitude will be propotiopnal to time - given the integrator is up to the task - which should be doable.

The usual solution is to use a high purity sine source which will produce a known histogram.

I've seen both as recommended tests, the ramp is usually used when low frequencies or DC performance is the prime concern.

[Kleinstein]

With a relative slow, high resolution test a histogram test is not really feasible: it just takes to much time. With some some 1 reading per second, 1 million codes to test and some 100 counts per bin needed for a useful statistics it takes ages to complete and drift would ruin things. The histogram method can still work for a more local part. Here it can help to have something like a triangle and 2 superimposed offsets to check if errors come from the triangle or the ADC.

Generating a high quality sine or ramp of the required quality is also very tricky if not impossible for the required low frequency (e.g. low or below mHz range - with lower case M !).  For the no so high end MCP355x, the more realistic way would be a PWM based DAC (e.g. a little like the Fluke 5700), that with some care and after some tests may show sufficient linearity. For testing one could use an independent shift to see if the observed error curve moves like the DAC or ADC.

The test with the added differential amplifier to suppress the common mode would still measure a combined effect of the amplifier INL and common mode errors and the ADC. At the ppm level OPs are no necessary ideal in all aspects and even resistors may show an effect of self heating. At least there is less chance to get some intrinsic error canceling for the ADC. The errors at the OPs have a chance to partially cancel, but this would be a good thing.

[MasterT]

Generating a high quality sine or ramp of the required quality is also very tricky if not impossible for the required low frequency (e.g. low or below mHz range - with lower case M !).  For the no so high end MCP355x, the more realistic way would be a PWM based DAC (e.g. a little like the Fluke 5700), that with some care and after some tests may show sufficient linearity. For testing one could use an independent shift to see if the observed error curve moves like the DAC or ADC.

In essence, to test good quality ADC get even better quality DAC. Can't find - build one.  Nothing new here.

The test with the added differential amplifier to suppress the common mode would still measure a combined effect of the amplifier INL and common mode errors and the ADC. At the ppm level OPs are no necessary ideal in all aspects and even resistors may show an effect of self heating. At least there is less chance to get some intrinsic error canceling for the ADC. The errors at the OPs have a chance to partially cancel, but this would be a good thing.

I'm aware that having buffer I measure combined INL both, buffer & ADC. This is why LME49721.  I have also MCP6D11,

• Low Distortion (2V p-p , 10 kHz):
- HD2: -138 dBc
- HD3: -137 dBc

At DC likely to have better than -140,  or required  0.1ppm. The technical problem I see, that 2V p-p . Same shit with THS4531 "THD: –120 dBc at 1 kHz (1 V RMS , R L = 2 kΩ)"  I'n not gonna to bring conspiracy theory into discussion, would check if can build diff amplifier with real R-2-R outputs (within 50 mV) and -140 dBc. It would not be soon.

 Results with LME49721 simply confirmed that MCP3550 is truly differential.  And if I failed to invent diff buffer, that  nobody else was  able  to create, than I don't need one

[MasterT]

After a lot of measurements I came to conclusion, that my diff - in / diff - out amplifier shown above indeed has some non-linearity issue, well above than ADC under test itself. 
 Thinking about a test setup, based on two voltage sources and measuring V1 & V2 separately, and than in series V3, nonlinearity easily calculated : INL = V3 - (V1 +V2).  The main technical problem is commutation of voltage sources, it requires to have different power sources OR diff-in / diff-out amp.
 If I replace V1 & V2 voltages by I1 & I2 currents than everything become very simple.  Circuits shows 4 switches, working in pairs. 
The idea is the same, INL = I3 - (I1 + I2) .
Results:

15:52:47.806 -> state: 0      mVl-1: -1.931799
15:52:49.034 -> state: 1      mVl-1: 0.000104
15:52:50.264 -> state: 2      mVl-1: -1.933375
15:52:51.459 -> state: 3      mVl-1: -3.865284

15:52:51.459 ->    Diff_x (uV): 6.44   dif-avg: 10.78   INL-a: 1.32

You can see 10.78 uV that translates to 1.32 ppm with 4.096V reference voltage.
To verify if there is current-voltage (inverters) non-linearity , I swapped ADC polarity a few times,  and didn't notice, at least above noise, about 0.1ppm as intended.