Two IC's outputting at the same time: Damage or Not?

[alm]

The TI "Designing with Logic" document, linked to several times in this thread including in the second post by the original poster, actually has a fairly detailed discussion of bus contention in section 7, including a thermal analysis.

[Zero999]

The TI "Designing with Logic" document, linked to several times in this thread including in the second post by the original poster, actually has a fairly detailed discussion of bus contention in section 7, including a thermal analysis.

But we don't know that's what the original poster is dealing with.

It seems more like he's talking about connecting two outputs in parallel to power a device such as a buzzer or bright LED, rather than using a discrete transistor. This may be fine for logic gates, such as the 74HC14, as long as the inputs are hard wired together but may cause smoke in an MCU, during start up or in the case of a software fault. I don't know about FPGAs or CPLDs though.

[PauloConstantino]

but Back to the original topic,

...

In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.

If you are preventing the outputs from contending then there is something wierd with your logic. If both of your outputs will always be in the same state then one of them is redundant. 

Have you ever heard of something called a bus ? Probably not. So let me explain it to you.... in a bus, multiple outputs are connected together, and only one of them is active at a time. So you prevent them from contending and having two of them output at the same time. Hence why I "prevent" them from contending.

There's a short period in buses when outputs might contend, since one if being switched on and the other off, there's some intersection unless you prevent it. I prevent it by adding a wait state so that both are off for 1 clock cycle. Which is a slow solution. If I remove this solution then the circuit becomes faster (no wait state), but then they might contend for a few nanoseconds. Hence my original question. 

[capt bullshot]

I guess, this thread would have been a single pager with one or two replies if you'd stated this in our original post 

Yes, it's quite normal to have short overlapping of the driving pins in a bus system, it doesn't harm the ICs because of the short duration, but it may cause all kinds of EMC related problems due to the high current spikes. Just go and test it.

[EEVblog]

but Back to the original topic,
my question was about shorting two IC outputs together. In this case then, it won't be safe because the maximum currents are undefined apparently.

Correct.
Actually, they aren't entirely undefined, you can kinda guestimate the output MOSFET resistance based on the different Vol and Voh values at different output currents. But it's not going to be linear.

In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.

If you are preventing them from contending then that's fine, you can tie the output, and in fact thatis common practice to get more output current capability. e.g. putting two or more inverters in a 74HC04 package in parallel in order to get more output drive. This is even shown in many datasheets.

I thought that because the max output sourcing was 25mA, and the max out sinking was also 25mA, that this meant I could connect them together. But since this is just the max safe level, I really can't unless I put a resistor there.

Putting outputs in parallel do a pretty good job at current sharing, you don't need current sharing resistors.
Just be aware that there also a maximum total sluppy current that comes into play.
e.g. if you have 6 x 25mA outputs in parallel and your maximum power pin current is 100mA, 100mA  is the maximum you should draw.

[PauloConstantino]

Yes i'm not talking about parallelling the same kinds of gates to generate a higher current. I was talking about bus contention...

However this has generated interesting responses.

I think given the inductances and capacitances of the traces, it might or might not damage the IC's. It would depend on the impedances of the traces and the actual period of time the IC's are contending. Who knows 

[EEVblog]

Have you ever heard of something called a bus ? Probably not. So let me explain it to you.... in a bus, multiple outputs are connected together, and only one of them is active at a time. So you prevent them from contending and having two of them output at the same time. Hence why I "prevent" them from contending.

That is called tri-stating outputs and is an entirely different thing to what has been discussed here because you failed to mention tri-state at all.

[EEVblog]

Yes i'm not talking about parallelling the same kinds of gates to generate a higher current. I was talking about bus contention...

http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

Page 19

[PauloConstantino]

but Back to the original topic,
my question was about shorting two IC outputs together. In this case then, it won't be safe because the maximum currents are undefined apparently.

Correct.
Actually, they aren't entirely undefined, you can kinda guestimate the output MOSFET resistance based on the different Vol and Voh values at different output currents. But it's not going to be linear.

In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.

If you are preventing them from contending then that's fine, you can tie the output, and in fact thatis common practice to get more output current capability. e.g. putting two or more inverters in a 74HC04 package in parallel in order to get more output drive. This is even shown in many datasheets.

I thought that because the max output sourcing was 25mA, and the max out sinking was also 25mA, that this meant I could connect them together. But since this is just the max safe level, I really can't unless I put a resistor there.

Putting outputs in parallel do a pretty good job at current sharing, you don't need current sharing resistors.
Just be aware that there also a maximum total sluppy current that comes into play.
e.g. if you have 6 x 25mA outputs in parallel and your maximum power pin current is 100mA, 100mA  is the maximum you should draw.

Fantastic! Not everyday you have Dave answering your threads

Thanks Dave. They were thinking I was talking about paralleling gates to generate more current but I was actually talking about bus contending...

I'd like to know what are the factors that come into play if you have outputs going into the same bus "bit". How likely they are to contend... And I've been thinking it depends on the impedances of the lines as it takes a while for the currents to get going, and also on the actual period the outputs are contending... What would be a good way of determining the likelihood of damage...

If I have a few control signals which tell each output whether to output or not, then if we consider the delays of the traces carrying these control signals, then the difference in (delay between the two IC's plus the propagation delays of each IC) will be equal to the amount of time they are contending in the bus... But then we need to also consider the impedances of the traces from the outputs of each gate to the bus...

What do you think the best solution is Dave?   

[PauloConstantino]

Have you ever heard of something called a bus ? Probably not. So let me explain it to you.... in a bus, multiple outputs are connected together, and only one of them is active at a time. So you prevent them from contending and having two of them output at the same time. Hence why I "prevent" them from contending.

That is called tri-stating outputs and is an entirely different thing to what has been discussed here because you failed to mention tri-state at all.

Yes I guess I failed at that Dave mate  . I wanted to focus the attention to the actual contending of the two outputs rather than tri-stating principles. Because once the IC's are contending, tri-stating doesn't come into play. But I have mentioned it finally. 

[helius]

There are two basic ways of preventing electrical contention (where one driver pulls a wire high at the same time another is pulling it low).
The first is a static method that ORs together all the drivers on the bus. Each driver is open-collector output, with a pull-up resistor at the end of the bus. Since each driver only pulls low for 0 and is high-Z for 1, the short circuit condition can never occur.
In the second method, the output enables of the bus drivers are gated by a signal that this particular driver has exclusive access to the bus. The protocol to select which driver has access is called arbitration. As long as every driver on the bus satisfies the protocol, it will never occur that more than one tries to drive the bus at any particular time.
Real systems use a combination of both methods, for example the arbitration protocol may use open-collector signals. This is all treated by basic computer design texts.

[PauloConstantino]

There are two basic ways of preventing electrical contention (where one driver pulls a wire high at the same time another is pulling it low).
The first is a static method that ORs together all the drivers on the bus. Each driver is open-collector output, with a pull-up resistor at the end of the bus. Since each driver only pulls low for 0 and is high-Z for 1, the short circuit condition can never occur.
In the second method, the output enables of the bus drivers are gated by a signal that this particular driver has exclusive access to the bus. The protocol to select which driver has access is called arbitration. As long as every driver on the bus satisfies the protocol, it will never occur that more than one tries to drive the bus at any particular time.
Real systems use a combination of both methods, for example the arbitration protocol may use open-collector signals. This is all treated by basic computer design texts.

Howdy.

Bus arbitration is used on external buses. Have you seen it used internally in a CPU's data bus? That's where I am concerned. Firstly most IC's don't have open drains or collectors, second it would be rather slow to have an internal protocol for a CPU's internal databus.

Anyways bus arbitration is a good concept, but I've not seen it used inside a CPU's internal databus. if you have I'd like to know.

[Rerouter]

It comes down to the data rates your after, Canbus is an example of a bus that can handle multiple devices outputting at the same time, and can handle data rates over 1Mbit at a few meters distance.

If your looking more at an older CPU with address decoding for a bus, then in general there is 1 master, and peripherals on the bus that are used to talk to other things, so the cpu master would select a new address, the decoder would disable the old device, and enable the new, the master would wait a number of cycles then change the bus from tristate to active and communicate with that peripheral.

Even if you had a secondary processor it was generally slaved to the master, you see the same occuring in modern MCU's, they may have multiple independant DMA channels, controlled by a DMA controller, but the master processor configures the dma peripheral then hands off that connection to it, Its still acting under the master, even if its a seperate peripheral now controlling the bus, the processor waits until the peripheral returns a completion state, then retakes control.

[PauloConstantino]

It comes down to the data rates your after, Canbus is an example of a bus that can handle multiple devices outputting at the same time, and can handle data rates over 1Mbit at a few meters distance.

If your looking more at an older CPU with address decoding for a bus, then in general there is 1 master, and peripherals on the bus that are used to talk to other things, so the cpu master would select a new address, the decoder would disable the old device, and enable the new, the master would wait a number of cycles then change the bus from tristate to active and communicate with that peripheral.

Even if you had a secondary processor it was generally slaved to the master, you see the same occuring in modern MCU's, they may have multiple independant DMA channels, controlled by a DMA controller, but the master processor configures the dma peripheral then hands off that connection to it, Its still acting under the master, even if its a seperate peripheral now controlling the bus, the processor waits until the peripheral returns a completion state, then retakes control.

Maaaate I mean the internal cpu data buses m8. The buses where internal registers output to m8.

[Gyro]

Bus arbitration is used on external buses. Have you seen it used internally in a CPU's data bus? That's where I am concerned. Firstly most IC's don't have open drains or collectors, second it would be rather slow to have an internal protocol for a CPU's internal databus.

Anyways bus arbitration is a good concept, but I've not seen it used inside a CPU's internal databus. if you have I'd like to know.

You won't find any contending gate outputs inside an IC either.

I still can't understand what you're trying to achieve. Contending gate outputs will produce an invalid (unuseable) logic level regardless of the possible damage. You say that the gate outputs won't contend but if they always output the same state, then something is redundant. The only other reason for paralleling outputs in the same state to achieve increased current drive (as Dave mentioned) but you say you're not doing that either.

What is it that you're actually trying to achieve?

EDIT: Scrub that - I see that you are worried about transient contention on state changes (yes or no?). In that case you will need to look at how whetever you are driving will handle the indeterminate logic levels, unless it is clocked downstream.

[Fungus]

What is it that you're actually trying to achieve?

Yep. What are you expecting to see on the output? It can't possibly be anything useful.

[helius]

Bus arbitration is used on external buses. Have you seen it used internally in a CPU's data bus? That's where I am concerned. Firstly most IC's don't have open drains or collectors, second it would be rather slow to have an internal protocol for a CPU's internal databus.

Anyways bus arbitration is a good concept, but I've not seen it used inside a CPU's internal databus. if you have I'd like to know.

In a simple CPU, there is a single sequencer that controls every other component. So it's not like the situation with several I/O cards that need arbitration to decide who will be master; the CPU sequencer is always the master. The timing diagram will be designed so that the sequencer disables the previous output to a bus on one cycle, and enables the new output on a later cycle, preventing both from driving it at once. This is critical because the internal gates are not latchup protected! Making sure that these timing constraints are maintained through voltage and frequency variations is extremely important and will be fully simulated. Each full cycle is usually split into several phases to make this sequencing easier.
In more complex multi-core processors it's more common to use crossbars and unidirectional links, rather than busses, to avoid the turnaround time when the bus must be inactive.

[PauloConstantino]

Bus arbitration is used on external buses. Have you seen it used internally in a CPU's data bus? That's where I am concerned. Firstly most IC's don't have open drains or collectors, second it would be rather slow to have an internal protocol for a CPU's internal databus.

Anyways bus arbitration is a good concept, but I've not seen it used inside a CPU's internal databus. if you have I'd like to know.

You won't find any contending gate outputs inside an IC either.

I still can't understand what you're trying to achieve. Contending gate outputs will produce an invalid (unuseable) logic level regardless of the possible damage. You say that the gate outputs won't contend but if they always output the same state, then something is redundant. The only other reason for paralleling outputs in the same state to achieve increased current drive (as Dave mentioned) but you say you're not doing that either.

What is it that you're actually trying to achieve?

EDIT: Scrub that - I see that you are worried about transient contention on state changes (yes or no?). In that case you will need to look at how whetever you are driving will handle the indeterminate logic levels, unless it is clocked downstream.

 

[Gyro]

What is it that you are trying to achieve?
Is your problem transient contention in asynchronous logic? Yes or no?
If not, then what?

Are the outputs tristate logic or not? it doesn't seem clear from your previous replies.

[KL27x]

Firstly most IC's don't have open drains or collectors

All microcontrollers have as many potentially open-drain outputs as they have tristate IO pins. Some even have their own pullups.

[PauloConstantino]

What is it that you are trying to achieve?
Is your problem transient contention in asynchronous logic? Yes or no?
If not, then what?

Are the outputs tristate logic or not? it doesn't seem clear from your previous replies.

I have an internal CPU data bus (I've built a cpu from scratchy), which has various registers outputs connected to it. At each clock cycle one of them at most is outputting into this bus. I prevent them from being active at the same time even for a few nanoseconds by having a null state where no output is active at all, after which one of them will be active, but this eats up 1 whole CPU clock cycle, which at 5MHz is not much but still adds up.

I was thinking if I would be able to remove the wait state, if the overlapping period is in the tenths of a nanosecond or something, because wire impedances might just delay it so that the outputs never really contend..... do you know? 

[Gyro]

So the outputs onto this CPU data bus are tristate outputs, not ordinary gates? (I think most of had the understanding that you were talking about ordinary gates, NAND NOR , whatever).

If they are tristate and you know that the overlap is really in the order of a nanosecond then there shouldn't be a problem at all. I think all CMOS ICs (did you say what logic family?) draw a supply current spike as their output FETs change state anyway.

It would help if you say exactly what device part number(s) these outputs are from.



EDIT: To save time...

If it is a tristate bus constructed using breadboards and wires (as your Homebrew CPU thread), your biggest problem will be ringing and ground bounce, not contention. Any contention might make the ringing worse though. You may be able to improve this by adding low value resistors in series with each output maybe 47 - 100R (nothing to do with current limiting, just to damp the ringing).

Of course you will  need to leave enough time for the bus lines to settle before reading them with another input, but that is not a device safety issue.

[C]

All logic has an output type.

With Tri-state logic output you enable only one output at a time.
You have some Tri-state time when changing outputs.

With Open Collector logic you can enable as many outputs as you want. Logic can only create a Low level with resistor pull up creating the high level.

With standard logic you connect one output to one or more inputs of another gate.
If you have outputs then you use a data selector like 74HC157 to pick the one you want.
 

[KL27x]

To add to that, some logic chips might have digital hi/lo output only. But many, many IC's come with open drain output variants. And if they don't, there are a host of buffer/inverter/gate/logic and other generic chips (which while not specifically made to do the job, will do it) that can be used to convert the signal to open drain. If you want to get primitive, you can use descrete transistors and pullup/downs. This is a common need for such problem as you have, plus for voltage translation and probably other things I haven't even considered, yet.

[PauloConstantino]

Last two posts are most useful!

Both using multiplexers and open drain buffers are great and neat solutions to this problem.

Appreciated!