I could be wrong, but I imagine the maximum output capability of a solid state device (as stated in the datasheet) may be limited by not only physical damage, but by what it can output and still maintain the defined voltage level for the logic levels as defined for that logic family and voltage.
For instance, CMOS 5V and 3.3V logic high output might be defined as minimum of 2.4V. And output low might be defined as maximum of 0.5V. (For TTL, these levels are different. For 1.8V CMOS, obviously, the levels are different).
If, due to the circuit designer's choices, the output current were to exceed this maximum, several things could happen, depending on what Vdd you are running at and/or what duty cycle (if output is switching intermittently). This might include damage to the device. Or just a saggy signal that doesn't meet spec, due to voltage drop across the output transistor and bond wire.
If you shorted the two outputs together, BTW, you will most certainly have no ill effect if is very brief and low duty cycle. You might want to beef up the decoupling caps to prevent noise coming back onto the rail. And the voltage you get at the node while it happens is going to be anyone's guess. You'd have to measure it, if it mattered. You'd be making a resistor ladder with the output transistors of the two pins... and as things heat up, it may change. But I'd go so far as to say, the average logic chip or microcontroller can't instantly burn a pin. The output impedance is just too high. It would take a significantly long pulse to cause damage even tied directly to Vdd or Vss. IOW, the max pulse current can't be exceeded short of connecting to a voltage higher/lower than the supply (and if ESD diodes were not there). Connected to another output pin of similar impedance, it might take on the order of millisecond or seconds... it might even cause no damage, indefinitely (when done within specified temperatures, and considering 5V supply or lower). This is just guessing, of course. These things aren't available to look up in the datasheet.
Maximum pulse power output will be when the load impedance matches the output transistor (and bondwire) resistance. Maximum pulse current may go higher, yet. But your voltage will be in the gutter at that point. At maximum pulse current, your output high might actually be a logic low. And vice versa.