Two IC's outputting at the same time: Damage or Not?

[sokoloff]

Anyways, I'm done with this thread now thanks.

You're not the only one.

[Rerouter]

now with a better understanding of why the rating exists (power dissipation) you can generally run higher currents so long as you reduce your duty cycle, e.g. 40ma at 45% PWM. to keep your average current below that 20mA, again it comes down to what you are hoping to accomplish.

[MK14]

Anology:

The UK council, may say that we can put out an ABSOLUTE MAXIMUM of two rubbish bags in the street, each week, and NOT get prosecuted or fined.

But as a minimum we can put out at least two bags and a lot more. Maybe 100 bags of rubbish/trash.

I.e. The absolute maximum, can be (in some cases) exceeded. It just might get you into trouble with a fine from a council, or the chip may malfunction or be damaged etc.

[PauloConstantino]

but Back to the original topic,

my question was about shorting two IC outputs together. In this case then, it won't be safe because the maximum currents are undefined apparently.

In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.

I thought that because the max output sourcing was 25mA, and the max out sinking was also 25mA, that this meant I could connect them together. But since this is just the max safe level, I really can't unless I put a resistor there.

Oh well, pirates

[Richard Crowley]

Perhaps the big question many of us are wondering is WHY do you "really want to do this"?

There are open-collector gates which allow you to create a "wired-OR" node.  If you stretch out that node, you can call it a "bus". 

https://en.wikipedia.org/wiki/Wired_logic_connection

And there are tri-state gates which allow outputs to take turns driving a node. But never more than one at a time.

But WHY one would want to connect ANY two outputs together that may have different states is simply incomprehensible to me.  If one gate says 1=high and the other says 0=low, how is that supposed to work?  Are you creating some sort of self-destructive device of some kind?

If this question was answered somewhere already, apologies.  Perhaps someone can reply with a concise answer.

[PauloConstantino]

Anology:

The UK council, may say that we can put out an ABSOLUTE MAXIMUM of two rubbish bags in the street, each week, and NOT get prosecuted or fined.

But as a minimum we can put out at least two bags and a lot more. Maybe 100 bags of rubbish/trash.

I.e. The absolute maximum, can be (in some cases) exceeded. It just might get you into trouble with a fine from a council, or the chip may malfunction or be damaged etc.

MK, you are confusing minimum with maximum again. As a minimum you can put out zero bags. Minimum is minimum. I think what you mean is that the minimum number of bags you can put out, more than which you get fined, is 2 bags. But then you don't need the word minimum. You use maximum for this. The maximum bags after which you get fined is 2.

You use minimum to speak of lower boundaries, lower than which something (bad) happens. In this case we don't care about lower currents, we care about higher currents or bags, so we use maximum. Minimum has no bearance in this.

But the plain, flat minimum you can put out is zero.

[MK14]

but Back to the original topic,

my question was about shorting two IC outputs together. In this case then, it won't be safe because the maximum currents are undefined apparently.

In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.

I thought that because the max output sourcing was 25mA, and the max out sinking was also 25mA, that this meant I could connect them together. But since this is just the max safe level, I really can't unless I put a resistor there.

Oh well, pirates

You have pretty much nailed it and got it EXACTLY right now!

[MK14]

Anology:

The UK council, may say that we can put out an ABSOLUTE MAXIMUM of two rubbish bags in the street, each week, and NOT get prosecuted or fined.

But as a minimum we can put out at least two bags and a lot more. Maybe 100 bags of rubbish/trash.

I.e. The absolute maximum, can be (in some cases) exceeded. It just might get you into trouble with a fine from a council, or the chip may malfunction or be damaged etc.

MK, you are confusing minimum with maximum again. As a minimum you can put out zero bags. Minimum is minimum. I think what you mean is that the minimum number of bags you can put out, more than which you get fined, is 2 bags. But then you don't need the word minimum. You use maximum for this. The maximum bags after which you get fined is 2.

You use minimum to speak of lower boundaries, lower than which something (bad) happens. In this case we don't care about lower currents, we care about higher currents or bags, so we use maximum. Minimum has no bearance in this.

But the plain, flat minimum you can put out is zero.

I now at least understand why I was confusing you. Minimum is often associated with the lowest value.

The main issue is really about the short-circuited outputs. The fact that I mentioned "minimum", is really a side issue. Not all the words and phrases I choose, in quick forum posts, are necessarily the best or perfect.

[MK14]

But the plain, flat minimum you can put out is zero.

The MINIMUM you can put out, is indeed, zero!

BUT, if you ask me to OVERLOAD (i.e. like a short-circuited output) the street with rubbish bags.
Because the limit is a maximum of two. We are probably safe to assume, that the lower limit of how many bags, we can squeeze into our street, is probably a MINIMUM of 2 (i.e. like starting from the absolute maximum current of 20 milliamps), but is a maximum of some unknown size, which is something like 100. If you measure the street, outside where a person lives and would dare to leave rubbish/trash bags out.

i.e. How many bags can we put out, maximally in our street, ignoring rules. Is a minimum of 2 (since we are allowed that many) and a maximum of some much bigger number, which could be 100.

EDIT: I definitely agree, that my starting point of the absolute maximum. May itself, sometimes be overly overoptimistic, and so the real minimum, may be lower or even zero. E.g. maybe there is only room for a single bag, or even no room for any bags, because there are too many parked cars outside, etc.
I.e. My use of "minimum", was not such a good idea or 100% correct. On reflection.

[Audioguru]

Texas Instruments has graphs of minimum and typical output current from 74HCxx ICs and with a 5V supply the typical shorted output current is 48mA sinking and is 55mA sourcing. The current is higher when the 5V supply is a little higher and some ICs produce much more current than the typical amount shown.

But the ICs have a maximum allowed output current of only 25mA.

[MK14]

Thanks, nice graphs.

Those graphs being labeled with "expected minimum", is a similar concept to why I was going from "Absolute Maximum", to a minimum type of term.
I'm surprised the currents are as low as that, e.g. 48 mA's.
I suspect the fastest/strongest logic series, would be much higher currents than those. Such as 74AC etc. Especially buffer or driver versions.

EDIT: Apparently, the short circuit current can be as high as 700 mA's (with a 5 output impedance).

E.g. With a SN74BCT25240, page 21
http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

[alm]

Well yes, that is a bus driver with an absolute maximum low state output current of 376 mA and a recommended low state output current of 188 mA. So clearly the short circuit current and output impedance would be lower . However, since they are in the same DIP/SOIC packages, I would expect them to overheat more quickly.

[Delta]

If one output is driving to 5v, and the other is driving to 0v, the result will some random voltage in between, and thus useless for driving a logic input.

WTF would be the point of that?  (That said, you are the type of person who chats with himself - see first two posts)

[Gyro]

but Back to the original topic,

...

In my circuits I prevent this from happening. I prevent them from contending, however, I could make the circuit faster if I removed the protection, hence why I wanted to know what happens.

If you are preventing the outputs from contending then there is something wierd with your logic. If both of your outputs will always be in the same state then one of them is redundant. 

[Fungus]

Because the maximum output/input currents in my IC's are 20mA, so where could the problem be ?

That's like saying "my car can rev to 7000RPM so where's the problem in driving around in first/second gear all day at 7000RPM with the needle on the red line? I'm driving within the car's specification, right?"

(assume that gasoline is free).

Question: Would you buy a second-hand car from somebody who drove it like that?

[rstofer]

That's like saying "my car can rev to 7000RPM so where's the problem in driving around in first/second gear all day at 7000RPM with the needle on the red line? I'm driving within the car's specification, right?"

(assume that gasoline is free).

Question: Would you buy a second-hand car from somebody who drove it like that?

Back in the day, we used to joke about selling off our cars after using them for drag racing.  Only 5000 miles!  Of course it was 1/4 mile at a time...

Thevinin Equivalent Impedance...

If the OP wants to know the output impedance of a logic gate, connect a resistor to ground, say 100 Ohms, and measure the voltage at logic 1 along with Vcc.  Most of the voltage drop will be across the resistor but some will be across the internal impedance.  Do some number crunching and you have the internal impedance.
 
Turn the resistor around and connect it to Vcc.  Repeat the number crunching when the gate output is logic 0.

I'm not going to do the math but the 100 Ohm resistor could also be chosen to come a lot closer to the pin maximum current.

[rstofer]

Thevinin Equivalent Impedance...

If the OP wants to know the output impedance of a logic gate, connect a resistor to ground, say 100 Ohms, and measure the voltage at logic 1 along with Vcc.  Most of the voltage drop will be across the resistor but some will be across the internal impedance.  Do some number crunching and you have the internal impedance.
 
Turn the resistor around and connect it to Vcc.  Repeat the number crunching when the gate output is logic 0.

I'm not going to do the math but the 100 Ohm resistor could also be chosen to come a lot closer to the pin maximum current.

That 100 Ohm resistor may be too low depending on the device.  Do the math first.

[KL27x]

I could be wrong, but I imagine the maximum output capability of a solid state device (as stated in the datasheet) may be limited by not only physical damage, but by what it can output and still maintain the defined voltage level for the logic levels as defined for that logic family and voltage.

For instance, CMOS 5V and 3.3V logic high output might be defined as minimum of 2.4V. And output low might be defined as maximum of 0.5V. (For TTL, these levels are different. For 1.8V CMOS, obviously, the levels are different).

If, due to the circuit designer's choices, the output current were to exceed this maximum, several things could happen, depending on what Vdd you are running at and/or what duty cycle (if output is switching intermittently). This might include damage to the device. Or just a saggy signal that doesn't meet spec, due to voltage drop across the output transistor and bond wire.

If you shorted the two outputs together, BTW, you will most certainly have no ill effect if is very brief and low duty cycle. You might want to beef up the decoupling caps to prevent noise coming back onto the rail. And the voltage you get at the node while it happens is going to be anyone's guess. You'd have to measure it, if it mattered. You'd be making a resistor ladder with the output transistors of the two pins... and as things heat up, it may change. But I'd go so far as to say, the average logic chip or microcontroller can't instantly burn a pin. The output impedance is just too high. It would take a significantly long pulse to cause damage even tied directly to Vdd or Vss. IOW, the max pulse current can't be exceeded short of connecting to a voltage higher/lower than the supply (and if ESD diodes were not there). Connected to another output pin of similar impedance, it might take on the order of millisecond or seconds... it might even cause no damage, indefinitely (when done within specified temperatures, and considering 5V supply or lower). This is just guessing, of course. These things aren't available to look up in the datasheet.

Maximum pulse power output will be when the load impedance matches the output transistor (and bondwire) resistance. Maximum pulse current may go higher, yet. But your voltage will be in the gutter at that point. At maximum pulse current, your output high might actually be a logic low. And vice versa.

[SL4P]

OPEN-COLLECTOR, or DIODE-OR can solve many problems.
Schottkys will help reduce forward drop

[AG6QR]

The absolute maximum ratings on the datasheet aren't limits which the IC itself enforces based on some sort of internal protection circuitry.  They are limits which, if exceeded, will destroy the device (maybe not always immediately, depending on how badly you violate the limits).  It's a contract between the chip makers and you, which says:  As long as you keep all values within the limits specified by "absolute maximum ratings", we guarantee the chip will perform its job as specified.  But if you ever exceed one of those "absolute maximum ratings", you're on your own, and we suspect the part may stop functioning.

If you want the IC to continue to work, then it's up to you, the circuit designer, to make sure that you don't allow the output to source or sink more than 20mA of current.  The IC itself won't help you limit its output to 20mA, except in the sense that the IC is likely to destroy itself if you try an exceed that 20mA

If you hook the output of a logic gate to the output of another logic gate, and you allow the logic gates to be in opposite states, what have you done to limit the current?  Nothing.  You can bet that the current will exceed the absolute maximum rating and one or both devices will be destroyed.

If you must wire two outputs together, then at least put an appropriate resistor between them to limit the current to the datasheet rating.

[alm]

Actually, they will tell you to avoid exceeding the recommended specs for a long time. And just to be clear, the IC is not guaranteed to work while you operate it beyond its recommended specs but below its absolute maximum specs. It will likely not meet its V_OH and V_IL specs over the temperature range. It is just guaranteed to survive (for a while).

[CopperCone]

Someone I know said that they used to do something like this on military electronics, to drive a motor on a aircraft "pod" (i.e. the thing under the wing with cameras that allow for target tracking/guidiance munitions).

I believe it was for Lockheed Martin.

They paralleled up a hex buffer (chip that had multiple gates).. said it was OK so long that you calculate the current limiting resistors., to limit output current from each device and prevent unequal sharing.  Not much R though.

I did not really think about this problem, a conversation just came to mind I had with someone a while back. I think the issue was that the devices will back feed each other due to different output impedance.

Might actually be high reliability, as you don't have all that current going through one junction. Kind of inefficient though due to the losses in the resistors. I think there was a specific reason it was done.

https://en.wikipedia.org/wiki/Targeting_pod

Might have been multiple chips

Things can get funny if you want reliable/weird specifications. Also fun to build and cool looking. Instead of the same old boring driver every time.


Reading this thread is painful. I don't know why, but my brain keeps turning off. I'd like to blame the datasheet authors for being cryptic.

[Zero999]

To answer the original question: it should be fine as long as you're 100% certain the outputs of the gates will always be the same. The trouble with this is each gate will be slightly different, even if they're on the same IC, so they won't all switch at exactly the same time. This will cause a higher current when changing state, than what's normally expected, but it shouldn't be too much of a problem at low speeds, as long as there's adequate supply decoupling. If the gates are all on the same IC, then the current sharing should be reasonable but still imperfect.

[CopperCone]

To answer the original question: it should be fine as long as you're 100% certain the outputs of the gates will always be the same. The trouble with this is each gate will be slightly different, even if they're on the same IC, so they won't all switch at exactly the same time. This will cause a higher current when changing state, than what's normally expected, but it shouldn't be too much of a problem at low speeds, as long as there's adequate supply decoupling. If the gates are all on the same IC, then the current sharing should be reasonable but still imperfect.

yes, you need to do a source impedance analysis. You might need to add inductance/capacitance/resistance.

This is a fun problem.

[joeqsmith]

I used to own a RadioShack color computer with I think a 6809.  RadioShack offered a technical reference manual for it.  In that manual, I will never forget they had a warning about using peek or poke in certain areas being able to damage the computer.  To save money, they had not fully decoded the bus.

This computer had no UART but they offered a modem.  Bit banged with assembler to get the timing tight enough for 300 BAUD? 

Then again, that has been many years ago.   Could be wrong.