frequency divider IC for PLL loop recommendations

[Etesla]

Hi all,

I'm trying to make a PLL controlled FM transmitter using readily available parts. I'm a fan of using some version of the CD4046 PLL as the central building block, with an external common collector colpitts oscillator with varistors as the VCO. For this to work at 100 Mhz, however, I need to capture the frequency of the output of the VCO and divide it down (the 4046 variants only work up to around 36 MHZ). I see that some circuits online (https://www.electronicsforu.com/electronics-projects/high-fidelity-fm-transmitter) use digital circuitry to divide down the 100 MHZ to something lower, but I'm skeptical that using the sinusoidal output of the VCO to trigger digital logic would work reliably. Overall, I need some integrated circuit that can divide down the frequency of the output of the VCO, preferably one that's designed for that purpose. With that in mind, here are my two questions:

1.) Is it common or advisable to just use digital logic to divide down an analog signal like in the linked schematic?
2.) Are there IC's that are intended to do this dividing down an analog frequency into a lower digital frequency that are in stock with distributors today?

Thank you!

[Benta]

Search for prescalers. ON Semiconductor is a good place to look.

[Theboel]

Hi,

I never use 4046 as VCO but MC12019 is a good candidate for Your prescalers

[Etesla]

The MC120XX prescalers were something I looked into. They seem to be the only 'prescaler' IC's on digikey. However, their minimum output frequency was 100 MHz, and I'd prefer to be using the chip I choose well within its limits. The most attractive IC for this purpose I have found was the UPB571, but I can't find it in stock anywhere. If anyone knows an IC like the UPB571 with similar characteristics in terms of sensitivity, frequency range, and division factors that's in stock, that's really what I'm looking for. I think they're called "dual-modulus prescalers" in general, but there's no subcategory for that on the websites of distributors...

[Benta]

Sorry for my bad advice. It seems that both ON and NXP have killed off the MC120xx prescalers. I wasn't aware of that.

[duak]

Etesla,

I looked at the data sheet for the MC12093, that is hopefully representative of the series.  Reading between the lines I think the low frequency limit of 100 Mhz is a result of the extended rise and fall times if a sine wave is used.  I expect that if the sine wave is squared up by an amplifier and voltage clamp, the prescaler will operate correctly at lower frequencies.  These series of chips are implemented in ECL that, unlike TTL or CMOS, are not saturating and don't really have much voltage gain.  Any input signal that has slow transition times relative to the switching times of the circuit, as does a sine wave, will be susceptible to induced noise or to misinterpretation by different elements in the chip.  It's too bad the data sheet doesn't seem to specify maximum input rise and fall times, as do most, if not all other digital chips.

BTW, do you have a particular divider design you'd like to implement?

[Etesla]

I would like to avoid adding another amplifier / buffer stage between the VCO and the prescaler just for the sake of simplicity. I planned on using flip flops for division at the 100 mhz level (74ac74), and counters to get better control of the division once the frequency is low enough (4060). I got these idea's from this schematic: (https://www.electronicsforu.com/electronics-projects/high-fidelity-fm-transmitter). Interestingly this schematic shows the 74ac74 taking the clock directly from the VCO through C3, biased to 2.5V with R4 and R5. I'm wondering if this method of clocking the 74ac74 could reliably work in real life...

[fourfathom]

 You might want to look at the ON Semi NB3N502 clock multiplier chip.  It's not exactly what you are looking for, but it might help you with your solution.

[iMo]

I would highly recommend you to use modern "all-in-one" PLL chips today. There is a plethora of those available from almost all vendors (ADI, Maxim, TI, ON,..).
With 4046 you would need two dividers - for the frequency step (ie 10kHz), and the 100MHz/N(N+1) prescaler.
Also with PLL you need a special modulus divider - like divided by 64 or 65.
For example I was using TBB206+MB504 64/65 prescaler decades back..

[duak]

Etesla,

If you look at the data sheet for the 74AC74 you'll see that the CLK input is buffered by an inverter:  Page 2 of http://www.ti.com/lit/ds/symlink/sn74ac74.pdf.  This inverter will amplify and square up the CLK for the following circuitry.  If you look at the dt/dV spec on page you'll see that as long as the transition time per Volt is 8 ns or less, and the high and low level input voltages are met, you'll be fine.  To meet this you'll need at least 2.2 Vp-p but more would be better.

A rough approximation is dt / Vp-p =  (1 / (2 x frequency)) / Vp-p
 for 88 MHz I get  2.58 ns / V, so it should be OK.

I don't think a CD4060 is capable of 24 MHz operation.  I think the designer meant a 74HC4060.

Given the crystal frequency and the divider moduli, this will operate at 96 MHz, which is not an FCC channel.  Many synthesized tuners will probably not be able to receive it correctly.  Is his OK?