What is the role of Q3 in this LS TTL schematic?

[VinzC]

Hi again.

Out of curiosity I wanted to check again the internals of Low Power Schottky TTL circuits and I stumbled upon this schematic:

I think I overlooked that but now I wonder: what is Q3 doing here? There is a resistor in standard TTL instead of this transistor, so what is its role, exactly?

Thanks in advance for any hint/info.

[BILLPOD]

Good Morning Vinz, I am curious what xistor Q1 is, that has 2 emitters

[edavid]

Q3 is an active pulldown that turns Q6 off more quickly than a resistor pulldown.

[moffy]

Good Morning Vinz, I am curious what xistor Q1 is, that has 2 emitters

Bipolar transistors can have multiple emitters, it's often used for current mirrors if say one wants twice the current out for that coming in, a matched transistor with two emitters will often be used. You could think of the analogy as two transistors with C-C and B-B but the emitters are separate.

[Zero999]

Good Morning Vinz, I am curious what xistor Q1 is, that has 2 emitters

It's equivalent to many transistors with their base and collector terminals joined. In some cases the transistors will be different sizes i.e.take up different amounts of room on the chip.

[bson]

Note also the Schottky transistors (with an S shape diode symbol).

[TimFox]

The multiple-emitter input transistors are why this type of circuit is called "TTL" (transistor-transistor logic), as opposed to "DTL" (diode-transistor logic).
Many BJT logic ICs are called TTL, when they are actually DTL with Schottky diodes.
A generic name for this style of IC is "current-sinking logic", where the current to be sunk is either diode current or emitter current, and the sink is a grounded-emitter NPN output (usually with active pull-up circuit).
The important feature of current-sinking logic is that the input-low input current is much higher than the input-high input current, as opposed to CMOS which is more balanced.

[VinzC]

Good Morning Vinz, I am curious what xistor Q1 is, that has 2 emitters

Sorry for being late, indeed that's a classic configuration encountered in transistor gate logic, as explained earlier.

Q3 is an active pulldown that turns Q6 off more quickly than a resistor pulldown.

That is interesting 
I don't remember ever seeing such a configuration. I only needed that answer to finally open the gates to literature on this topic (e.g. https://electronics.stackexchange.com/questions/676573), so thanks a bunch for the tip!

EDIT: If I were to give that setup a name I'd go for "active turn-off" as the symmetric version for a PNP transistor would be an active pullup instead (I guess).