![](https://www.richis-lab.de/images/transistoren/a27x01.jpg)
![](https://www.richis-lab.de/images/transistoren/a27x08.jpg)
![](https://www.richis-lab.de/images/transistoren/a27x02.jpg)
Let´s take a look into a SMY60, a Dual-p-MOSFET built by the Funkwerk Erfurt.
The SMY60 has no protection diodes. To protect the MOSFETs against ESD there is a copper clamp above the package shorting all pins. After soldering the SMY60 into a circuit you can remove the clamp.
K stands for a production in the year 1977.
(-25V/20mA)
![](https://www.richis-lab.de/images/transistoren/a27x03.jpg)
The datasheet shows that the bulk contacts of the two MOSFETs are connected but they are not connected to the source contacts.
Although it can conduct twice the current of the SMY51 (
https://www.richis-lab.de/FET09.htm) the gate capacity is a little lower: 10pF vs. 12pF. One explanation for the lower gate charge is that the SMY51 contains protection diodes.
![](https://www.richis-lab.de/images/transistoren/a27x04.jpg)
![](https://www.richis-lab.de/images/transistoren/a27x05.jpg)
The die was protected with some silicone like potting. It is 1,1mm x 0,9mm, a little bigger than the SMY51 but the sizes of the transistors are quite similar. The gate electrodes are a little less overlapping in the SMY60. That could be another small share to the smaller gate capacity. In the upper right area there are four squares to check the manufacturing quality. The 2222 shows the revisions of the masks.
The two MOSFETs are integrated side by side to get them most equal in terms of production and temperature. On the left side we have the bulk connection. This potential is guided around the die and between the two MOSFETs to get some shielding.
You can see the meshed drain and source areas. They are a little unsymmetrical and it seems there are different doping levels too. The datasheet states a Source-Bulk breakdown voltage of -15V and a Drain-Bulk breakdown voltage of -25V. The source area seems to be doped more heavily.
![](https://www.richis-lab.de/images/transistoren/a27x06.jpg)
![](https://www.richis-lab.de/images/transistoren/a27x07.jpg)
After removing some of the metal layer we can take a closer look at the MOSFET.
The field oxide (FOX) had been removed in the area where the MOSFET was integrated. The substrate is p-doped. The area of source and drain got n-doped. Between source and drain there is the p-doped channel left. The channel width is something around 8-9µm.
Left and right of the MOSFET there are vias to contact source and drain with the metal layer.
The yellowish part is the thin gate oxide (GOX). In this area the potential of the metal layer influences the resistance of the channel. In the areas around the GOX the silicone oxide is a little thicker but still thinner than the FOX.
https://www.richis-lab.de/FET20.htm ![Tweak :-/O](https://www.eevblog.com/forum/Smileys/default/smiliey_cal.gif)