By definition an FPGA is inefficient at use of silicon area. There is lots of overhead for the ability to route between the logic cells. There is overhead in programming that interconnect logic. Add to that the difficulty in using all the logic, by definition you will not achieve 100% utilization. (Unless we are discussing some academic exercise rather than a real project.)
In addition, with the overhead in an FPGA, this drives the total power consumption up, as the overhead to make it programmable takes power to drive.
In high volumes, an ASIC is cheaper. There is a whole business segment that takes FPGA designs, and turns them into ASIC's, as over some volume level, it pays to do so.
Sorry, but with the overhead in an FPGA, I don't see how you came to the conclusion they will overthrow ASIC's or processors.