The best schematic layout standards

[Mechatrommer]

I really hate what seems to be a recent trend of just dumping a load of symbols down, sticking some net names on and thinking that's Job Done.
OK for complex circuits, having wires drawn between all nodes can get complicated, but for simpler  ones it's just laziness, and makes it hard to read.
In particular it's very hard to see how many different places one net is connected to.

...I find a couple of pull up resistors attached by net labels sitting in the corner of the last page of their schematic

That is just unforgivable.

here... a gift for your pet hates (attached #258)... i dont call it laziness, i call it saving time during refactoring... work smart, not work hard. luckily i work alone as a hobbiest, not a pro with many colleagues, so i dont think i will hurt anybody... ie for my eyes only. but if someone need to understand my circuit, get along...

[radar_macgyver]

^^ I'm just going to look the other way and assume Mechatrommer is trolling 

I've started to make my schematic symbols for complex ICs indicate what they do internally. This is not always possible (for example FPGAs or microcontrollers) but for things like RF MMICs, it helps to understand the signal path if for example a mixer symbol internally shows the traditional RF mixer symbol, rather than a rectangle with some pins on it. Shown below is my symbol for an LMX2594 synthesizer.

[Scutarius]

I like the idea! I don't recall ever seeing that before.
Thanks for sharing.

[merport]

In ancient times, the engineer would hand draw the schematic, hand it off to a technician to prototype, evaluate. So I think readability and theory of operation awareness  where part of the process. Then the draftsman would get involved followed by the assembly people. Modern electronic interfaces and packaging have created a different process that relies on computer entry for most of the work flow.

I don't know what work flow standards there are in the EE world, but from reading comments here, the work flow is based around the development tools. So what to do. I guess have the software nag the EE that they are not using the proper style. Perhaps have a variety of style templates that can be build into the software.
 

[free_electron]

Here is the definitive , keep you nose clean , avoid trouble, guide to drawing schematics.

1) symbols have pins that represent physical pads on the board.
2) connections are made using WIRES between pins on a sheet.
3) netnames are just that : names to apply to a net as opposed to letting the machine use net_xxxx format. The name is there so you can find the bloody damn signal on the pcb layout.
4) netnames do NOT infer connection and should NEVER be used for such purpose. Anyone drawing schematics with netnames dangling directly off pins should be re-educated. if that fails : fired and prohibited from ever designing anything again.
5) read 4 again
6) connectivity leaving a page does so through a port or a power object. NOT through net-names ( read 4 again )
7) wires attached to a power port or port do NOT get a net-name. The port names the wire. you do not want to tie two different net-names to 1 wire ! that is asking for trouble
crossing wires NEVER connect. Connections are made only on T-junctions !
9) instantiated pages higher in the hierarchy use wires to connect ports together. of port names are identical on all sub-sheets there is no need to name the wire. If port names are NOT identical then the wire must be named.
10) Higher up names in the hierarchy override lower level names.

The above 10 rules will guarantee a clean ,readable, block reusable , design where you can do multichannel designs using <repeat> constructions  without running in to massive undetectable short circuits.

Do not try to outsmart the software ! you are only going to muck it up into a mess that is impossible to untangle unless you know what to look for. Every time a new guy shows up with questions like 'every time i do an update it removes a bunch of nets and loads different ones . on the next update it puts the old nets back and removes the new ones .. what is going on ? ' the answer is : you apparently do not know how to draw schematics.

if you are going to do multilevel hierarchy : use a strict hierarchy where power ports are restricted to the page they reside on.

an example :

Run a netlist and you will find that the centerpoint between the two transistors is tied to .... GND ! why ? because the wire has no name so it takes on the name of the port (GND). We also did an override on ISO_GND by naming it GND.
You will also find a big fat short between the gates , becasue they both get names GATE_DRV...
You have a half bridge that will bounce the ground of the control electronics up and down between +450 and -450 volts ! Now imagine someone making a 3 phase version of this .... all three phases are shorted , and shorted to the control ground. all the gates are shorted so all transistors fire at the same time. Power this thing up , fed from a 50Kwh Stationary storage LiIon pack and you will be lucky if they find your shoes , or any remains from the lab at all ...

[richard.cs]

I've started to make my schematic symbols for complex ICs indicate what they do internally.

I do this as much as possible, often there is a diagram in the datasheet which is a good example to work to, usually with some simplification. Some examples attached (and yes I have found occasion to use a 723 in the modern world).

Another pet hate that relates to symbols matching packages is components with several distinct sub-parts drawn as a single symbol. A dual transistor package with them both drawn as a single part so they can't be moved relative to each other just doesn't allow a sensible schematic in most cases.

[Chris56000]

Hi!

That's what I do with my Abacom sPlan 7 software – it was bought to document an already designed product for repair purposes, so I lift the i.c. internal block diagram from the datasheet (where it's not too complex!) and trace over it to produce the i.c. circuit symbol.

Far too many people who buy (or get bought for their job) multi–£K EDA tool licences still have the horrible habit of bunging down D.I.L. Symbols with the pins in the original order, so you end up with in omprehensible mazes of crossing wires, or they just give up with the pin stubs going nowhere and a load of equally incomprehensible labels on them!

If you look at a circuit diagram for an analogue CRT TV, or an old VCR, etc., it was virtually standard practice to show analogue i.c. devices in block form, and if the device designer made a good block layout to begin with, you can easily work out what the external components connected to the device do, which you can't do with Altium's & KiCAD's garish yellow boxes!

My standard for circuit diagrams was to aim for the quality of those produced by Thorn/E.M.I./Ferguson, the last of the large British Consumer OEM's, their diagrs were based on principles laid down in BS 3939: 1975 (and as amended) – if like me, your main need is documenting existing items for repair, (then unless you need to design/manufacture a complete new PCB, in which case you do need a complete EDA tool or online equivalent, e.g., easy EDA), use something like sPlan 7, or learn KiCAD (Udemy have had a £10 offer on a full Electronics & PCB course from time to time).

Another gripe is schematics with all the connection marks left on it, all the pins "1" and "2" on passive components, net labels cluttering it up everywhere etc., etc., you don't need all this rubbish on the final diagram – this is caused by not properly setting the display and print options after installation!

As to all the garish yellow i.c. boxes and symbols, etc., again I never use them, I make my own symbol based on the i.c. datasheet block diagram as described above!

And please, can we get out of this horrible bloody habit of using Times New Roman on Altium's drawings please? Chris Schroeder wrote in his book "Inside Orcad For Windows" (Internet Archive) –"serifs and other embellishments have no place on technical drawing lettering!"

Again this is because users are too lazy to set up the global system Font Options after installation – Altium and Orcad offer full schematic TTF support, so there's no excuse for not using proper CAD type lettering – these packages do add some to the "Fonts" folder when installed!

My best tip is to download as many free service manuals as takes your fancy, e.g., H.P., Tek, etc., and see how they do it!

Chris Williams