It seems like the bottom npn transistors are used as current source loads but how are the current values chosen for each stage?
You are correct they are current sink active loads for the respective transistors.
Choice of current is going to be based on having enough current to overcome any capacitance (intrinsic device, stray, next stage input) at the frequencies in question and also by the input impedance of the following stage (probably 50 ohms). For this kind of wide bandwidth circuit you'll generally throw as much as you can at it, but no more than you need to get the output impedance low enough to happily drive about 50 ohms impedance (and here we are definitely dealing with impedance as opposed to resistance and we
must take capacitances into account).
I thought that the current source values would be chosen such that the output of the two amplifiers would be ~0V when the input is 0V.
That's taken care of by the DC control loop set up by the preceding op amp, that you've omitted in your diagram. You can, however, still see the negative feedback limb of that being taken off from the output node. The DC input bias at the JFET gate will probably only be within a 100mV or so of zero, the op amp will take care of setting that at the right level for the output to be ~0V.
However, I'd assume that the bias currents would also have an effect on the bandwidth of each stage? I'd really appreciate any kind of input on how circuits like these are biased for applications where bandwidth is also important. It'd also be great if someone could explain the circuit that's attached or how it should be analyzed. Thanks!
The 3k01 and 2k resistors from ground to -5 form a voltage divider. This sets the V
BE of the two BC349 active load transistors (in combination with the 249 and 75 ohm emitter resistors) and hence sets the emitter currents to ~5mA and 15mA respectively.
From there, the top two transistors are a source follower and an emitter follower (connected very much like a Darlington pair would be) to provide masses of current gain and a voltage gain very close to one. Hence the impedance converter tag, very high input impedance (input DC bias current in the 10 pA region) and low output impedance (typically low enough to comfortably drive 50 ohms or thereabouts).
Most of the bandwidth comes from choosing source/emitter followers, which isolates drain/collector capacitance and avoids the Miller effect and just making sure that there's enough current drive at each stage to overcome intrinsic and stray capacitances.
A quick fiddle with SPICE shows the DC input impedance at the gate of the JFET to be 725Gohm, the DC output impedance to be 3.35 ohms at the emitter of the BTH10, and the overall DC voltage gain to be 0.93, all unloaded.