The U61000 is a 1MBit DRAM developed at the Zentrum für Mikroelektronik Dresden. It was never transferred to mass production. The so-called megabit chip has achieved a certain fame as it was one of the last prestige projects of the GDR semiconductor industry. Much of the following information comes from people who were involved in the development of the chip, including the project manager Prof. Dr. Bernd Junghans, the chief developer Dr. Jens Knobloch, the head of technology development Dr. Michael Raab, the director of research and development Prof. Dr. Dieter Landgraf-Dietz, the division manager Jörg Ludewig and Dr. Hans Becker, who did his doctorate in the field of the U61000.
The unusually large lid of the package is immediately noticeable. It covers almost the entire surface. The characters A2 show that the part was produced in February 1990. The 12 on the left-hand side indicates the slowest bin with an access time of 120ns. According to the datasheet, one faster bin was planned.
This diagram was taken from the study "Der Osten Deutschlands - ein Standort europäischer Elektronik-Industrie" written by Prof. Dr. Wolfgang Marschall. It shows the technological backwardness of the GDR semiconductor industry in an international comparison.
The table above, taken from the article "Die “technologische Lücke” - zum Rückstand der mikroelektronischen Industrie der DDR" published in 1998 in issue 25 of "Dresdener Beiträge zur Geschichte der Technikwissenschaften", is even clearer. According to the article, series production of the one-megabit chip in the GDR did not begin until five years after the international market launch. In addition to the technological backlog, the high development costs and the comparatively low quantities also meant that electronic components from own development and production were very expensive. Nevertheless, their own developments were necessary and sensible for the GDR, as integrated circuits were often on embargo lists and valuable foreign currency had to be sacrificed. At the same time, many different ICs were urgently needed for consumer goods, industry and, of course, the military.
If new processes are developed in the semiconductor industry that enable smaller structure widths, they are usually used to produce memory first. Memory has relatively simple, constantly repeating structures. It was therefore only logical for the GDR to further develop their memory technology. The process used in the U61000 is called CSGT5d: Complementary Silicon Gate Technology, technology level 5. The letter d probably indicates a variant of this process. In the publication "Looking back: Artwork and Mask Making in Dresden for the East German Megabit Chip Project" by Hans W. Becker, it is stated that "about 16" masks were used. Michael Raab, Head of Technology Development, also spoke of 16 masks (and 6 implantation steps) at the 19th Leibniz Conference in his lecture "Technologie der Mikroelektronik der Schlüssel für die digitale Revolution". In 1989, the journal "Mikroprozessortechnik" published a large article by Dr. Jens Knobloch with a little more detail. According to this article, three polysilicon layers and one metal layer were used to connect the 2,3 million components. A total of 430 sub-steps were necessary to produce the U61000. This article mentions 18 photolithographic structuring steps.
Of course, third-party samples were also analysed for the development of the U61000. The TC511000 from Toshiba was particularly important in this context. Siemens produced similar chips and had acquired a licence for them from Toshiba. The GDR's foreign intelligence service had even obtained documents on this megabit chip. However, it was not possible to build the U61000 on this basis, as it was necessary to work with the technologies and materials that were available. The basic architecture and functional blocks may have been inspired, but it was not possible to simply copy the Western product.
The Soviet Union was able to produce 256kBit memory before the GDR. However, when the GDR was able to hand over a 1MBit memory to the Soviet Union, unique parts of its own megabit memories were only available there. Moreover, these were not yet based on the more modern CMOS technology. However, the GDR used some specialised technical equipment from Western production, while the Soviet Union relied solely on its own production facilities (Source: Wafer stepper and megabit chip by Otto Bernd Kirchner).
According to Wikipedia, the U61000 was planned for use in the Robotron computers K1820, K1840 and EC1835, among others. Here you can see the K1822 workstation. This is a replica of the MicroVAX II from DEC. The corresponding MSC20 memory module is shown on the right. With 72 U61000, the plug-in card offers 8MB of memory.
The table above shows the different revisions of the U61000, some core specifications and who published the information. Before the better-known versions, there was the U61000T, which was later renamed U61000-0. This was the first draft of the megabit memory, which was finalised in December 1987. The first chips were available in April 1988, although they still contained bit errors.
With the knowledge gained from the U61000-0, the design of the U61000-1 was finalised in May 1988. This made it possible to produce the first bit-error-free chips in August 1988. In September 1988, the first samples of the megabit chip were presented to the public. The sub-variants U61000-1.1 and U61000-1.2 were then produced from this variant. Pilot production of the U61000-1.1 began in March 1989 and the U61000-1.2 was produced from September 1989 to March 1990. A total of 6.700 components were produced.
The dimensions of the U61000-1 were 12,8mm x 5,1mm. For use in expoxy packages, it was necessary to make the die a little smaller. For this reason, the design of the U61000-2 version was finalised in January 1989. Dimensions between 12,5mm x 4,4mm and 12,6mm x 4,5mm are specified for this and the two sub-variants 2.1 and 2.2. It was particularly important to reduce the width. Previous tests had shown that the dimensions of the storage capacitors could be reduced from 3,89µm x 9,00µm to 3,24µm x 9,00µm. This was certainly very helpful in this context.
Dr. Hans Becker states a yield of 10% and 20% respectively for the last two versions 2.1 and 2.2. According to various sources, the total number of U61000s produced must have been around 30.000.
The 19th Leibniz Conference included the presentation "Entwicklung des Megabitspeichers U61000 1986 bis 1990" by Dr. Jens Knobloch. It contains the table above, which shows the characteristic values of the pilot production. The targeted specifications were achieved and in some cases significantly exceeded. The yield was 9,5% and the necessary reliability was also demonstrated.
Inside the package, you can see how borderline large the die of the U61000 is. It is also noticeable that there is no thick protective layer on the silicon, as can be found on the U2164 (
https://www.richis-lab.de/RAM08.htm), for example. Such layers are often used in memories to shield alpha radiation. The package materials are never completely free of radioactive elements, whose radiation can lead to bit flipping. A certain degree of robustness against ionising radiation is achieved through the structure and arrangement of the storage cells. Dr. Jens Knobloch also describes in the article "Der Megabitspeicher U61000" in the journal Mikroprozessortechnik (issue 10, 1989) that potential barriers were incorporated into the U61000 under the memory capacitors and under the bit lines to reduce the effects of ionising radiation.
The lecture "Speicherchip-Packaging - die Technologielokomotive für das Back-end" by Jörg Ludewig is also part of the 19th Leibniz Conference. It includes a technical drawing of the package. The package had to be imported and was correspondingly expensive. A changeover to an epoxy package had to be made as quickly as possible.
The labelling shows that the potential Ubb is contacted at both edges. Ubb is the substrate potential that is not routed to the outside, but is only connected to the metal surface on which the die is located.
The dimensions of the die are 12,8mm x 5,1mm. This corresponds to the dimensions found in the literature for the U61000-1.
The image of the die is also available in a higher resolution:
https://www.richis-lab.de/images/RAM/13x04XL.jpg (28MB)
A stylised frog is depicted next to the designation U61000. The chief developer Dr. Jens Knobloch immortalised himself on his designs with this symbol.
The U61000 datasheet shows the memory interfaces. The ten address lines are used to first select the row and then the column of the memory.
The above block diagram can be found in the aforementioned article "Der Megabitspeicher U61000". Four 256kB blocks form the core of the memory. Each block has 512 lines. The line decoders each activate one line. Four times 512 sensor amplifiers analyse the four times 512 columns and then write the data back again. The column decoder selects one cell from each block. One of the four cells is then analysed for the output. As will be shown later, this representation does not quite correspond to reality.
For addressing, the ten address bits are stored once in the row address buffer and once in the column address buffer. The U61000 also contains a refresh control with an address counter. This function block makes it easier to update all data in the memory fast enough.
The potentials of the pins are easily found on the die (cyan). As can be seen in the drawing of the package, there is a bondpad on the left and one on the right that carry the substrate potential (orange). There are two unused bondpads on the upper edge. Another unused bondpad is located at the bottom edge (white). The signals of all three bondpads end in stubs. However, the structures contain provisions to connect the bondpads with the address potentials A0, A8 and A9. This was presumably intended to keep the option of using other package types with differently positioned contact surfaces.
The input protection circuit appears almost like a work of art. To a large extent, it corresponds to the protection circuit described in more detail in the U2164 (
https://www.richis-lab.de/RAM02.htm). Here, an additional transistor has been integrated close to the bondpad, which uses a metal strip as a gate electrode. This transistor only becomes conductive at exceptionally high voltages and then creates a low-resistance connection to the reference potential.
The die has a large number of testpads. These include 27 large testpads (red), which could also be contacted automatically. 82 significantly smaller testpads (yellow) allow internal signals to be contacted for more in-depth tests without having to modify the structures of the chip.
The large testpads often contact test structures, but not exclusively. The small testpads are mainly used as taps for internal signals.
The structure widths and the many layers make it difficult to analyse the circuit components precisely. However, the recognisable structures and the connections make it possible to understand how the circuit works in many places.
The large structures of the charge pump, which ensures a negative substrate potential, can be found in the upper right-hand area of the die. One might think that the upper area represents the associated clock generator. However, the clock generator actually appears to be located in the lower area of the die. This leaves open what function the upper circuit fulfils. Perhaps it is an adjustment/modification of the clock signal.
Here you can see the circuit at the bottom right of the die, which most likely contains the clock generator. The larger, upper part of the image contains large structures that could represent the resistors and capacitors required for a clock generator. The small, repeating structures could be the associated transistors. At the upper end of the image, four wider lines lead to the right, which appear to be clock lines.
The clock lines lead to the charge pump, among other things. However, the U61000 also requires a clock signal in other areas. Obviously, this is the address counter for regularly updating the data. However, the clock is also routed to the memory blocks. For this purpose, there is a circuit in each of the two right-hand corners of the die that looks like a driver. Here you can see one of the two circuits at the bottom of the picture.
The structure of the storage area cannot be recognised. The structures would still be large enough to resolve them optically. However, the many layers, which carry many lines in this area, create an unevenness in the surface that makes the image very confusing.
The word line (line selection, vertical) was mapped in the aluminium layer. The relatively low-resistance metal allows for long cables. The bit lines (column selection, horizontal) could be made shorter as a result. This is advantageous as it results in lower parasitic capacitances, which makes it easier to analyse the voltages, which are only slightly above 100 mV.
The image above is from the article "Der Megabitspeicher U61000" by Dr. Jens Knobloch. The four wiring layers ensure that the top view remains unclear even in the stylised representation. The cross-section is somewhat easier to understand. The first and lowest polysilicon layer forms the storage capacities with the n-doped areas in the substrate. The potentials of the word lines, which are distributed via the metal layer, reach the gate electrodes of the selection transistors via contact windows, which cannot be seen in the cross-section. The gate electrodes are structured with the second polysilicon layer. This is surprising at first glance. Normally, the highest demands are placed on the gate oxide of the transistors. One would therefore expect the gate electrodes to be manufactured first. In a DRAM, however, the storage capacity is more critical, which was probably the reason for producing it with the first polysilicon layer. The bit lines are located in the third, top polysilicon layer. As with the U2164, it contacts a point between two memory cells (
https://www.richis-lab.de/RAM02.htm).
Prof. Dr. Bernd Junghans and Dr. Michael Raab published the article "CSGT5 - eine moderne Basistechnologie fuer Hoechstintegration" in the magazine Jenaer Rundschau in 1989. It contains the stylised structure above and the SEM image of a polished section below. You can immediately recognise the irregular surface, which makes it difficult to resolve the structures optically.
The top image in particular shows more clearly where which areas are located and how they are structured. The substrate is coloured dark green at the bottom. The orange layer contains the doping, which results in conductive structures in the substrate and between which MOS transistors are created with a gate electrode. The black shaded material is the silicon oxide that serves to insulate the conductive areas. The first polysilicon layer is shown in dark brown. As described above, it represents the storage capacity. The second polysilicon layer in dark blue on the right is the gate electrode of the selection transistor. The left-hand strip has no function in this image. It merely leads to the next, shifted memory cell and forms the gate electrode of the selection transistor there. The third polysilicon layer is shown here in more detail. The image description explains that it is molybdenum silicide, which is located on a polysilicon base. The metal layer is coloured yellow.
As the structure widths are reduced, the resistances of the conductor paths and contacts between the layers become increasingly critical. For this reason, western megabit memories use titanium. Titanium reacts with silicon to form titanium silicide, which offers significantly reduced resistance. The GDR did not have titanium with a sufficiently high purity (99,9999%). It would have taken at least 5 years to produce such pure titanium. As an alternative, high-purity molybdenum could be used, which is also well suited to reducing the resistance of silicon. However, the structures produced with this material behaved differently. This was one reason why the known structures of western megabit memories could not simply be adopted.
The picture above is from the lecture "Entwicklung des Megabitspeichers U61000 1986 bis 1990" by Dr. Jens Knobloch. It shows the result of an element analysis on a section of the U61000. The substrate and the polysilicon lines consist mainly of silicon, which is shown in blue. The insulating silicon oxide is shown in red. The metal lines are green. The yellow-coloured molybdenum is clearly visible in the horizontal bit line.
There is another very interesting article in the Jenaer Rundschau from 1989: "Entwurf des Megabitspeichers" by Dr. Jens Knobloch, Prof. Dr. Wolf-Joachim Fischer, Stephan Dobritz and Andreas Scade. It documents, among other things, the reduction of structure sizes in the area of DRAMs with the image above. For the publication on this page, only the arrangement of the components has been slightly modified and the designations added. In some cases, only the functional areas of a structure have been coloured. This must be taken into account in order to understand the illustrations. The red areas represent the memory capacities. The selection transistor is located in the area coloured blue. Contact windows are coloured green. The metal layer is grey. A slightly darker blue colour has been chosen for the trench structure of the 4MBit DRAM.
The U256, a 16kBit DRAM, has a completely different structure to all subsequent memory technologies. The structure of the memory cells in the 64kBit DRAM U2164 has already been documented in detail (
https://www.richis-lab.de/RAM02.htm). The coloured illustration of the U61000 cell is easy to understand with the above basics. For the U61256 (
https://www.richis-lab.de/RAM09.htm), the illustration does not appear to be quite correct. According to this, the bit and word lines would be shown in the metal layer and would cross each other. However, as the U61256 only has one metal layer, this is not possible. Judging by the pictures of the U61256, the bit line is in the polysilicon layer. This would also fit in with the fact that the U61256 is often mentioned as an important step towards the U61000. The selection transistor of the U61256 is also shown too large.
The U61000 was to be the last DRAM with flat memory capacitors. The 4 MBit DRAMs already available internationally had already been converted to three-dimensional capacitors. A constant reduction in the size of the memory cells reduces the memory capacities in the first instance. This can be counteracted to a certain extent by increasing the capacitance density. For example, the dielectric in the U61000 is just 10nm thick. Nevertheless, the development is problematic. The leakage current does not decrease in the same proportion as the capacitance, so that the holding time of the information is continually reduced. The parasitic capacities in the evaluation path also become increasingly critical with smaller memory capacities. The memory capacity of the U2164 is still 50fF. No information can be found for the U61000, but for the 4MBit memory the aim was to achieve 40fF. As can be seen above, a trench capacitance was planned for this, i.e. a depression that increases the capacitance of the capacitor surface.
The diagram shown here is also taken from the article: "Entwurf des Megabitspeichers". There you can see how the area of a memory cell has been reduced over the generations. The two revisions of the 64kBit DRAM U2164 have already been documented (
https://www.richis-lab.de/RAM08.htm). As already described, it was possible to significantly reduce the memory cell area in the U61000 from version 1 to version 2. The 4MBit memory should again result in a very significant reduction in area requirements.
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