Hi guys,
right now, i try to design an full Bridge Class D Amp with ~100W/24V @8Ohm (I know, one of hundred thousand projects - sorry...
).
I finished all my calculations and started to simulate the power stage in LTspice and it works well as expected (in LTspice)!
But then, i did some "simulated" measurements and get shocked!
The switching frequency is about 250kHz (I would prefer up to 400kHz for the "physical" Amp)
My MOSFETS (IRFH5215) has needle peak (turn on) losses of up to 350W and (turn off) of up to 40W for ~10ns and less.
I even tried to reduce the peak current by an inductor in front of the Mosfets with turn on and off snubber without great success
Are those needle peaks of power losses acceptable for ~10ns @250kHz?
the Mosfets are driven by LTC4444 drivers (in the simulation) with an 10R resistor (turn on) at the Gate and in parallel (for turn off) a Diode with 2.2R in Series. Between Gate and Soure I placed an 4k7 resistor.
The Mosfet body diodes (both Mosfets hi and low) are bypassed with 30BQ060 schottky diodes. They get current peaks with up to 6A for about 800ns. The Datasheet of the 30BQ060 says I[f] average of up to 3A and I[fsm] up to 1200A @ 5ยต sinus. Is my selection suitable? (I guess (or better hope so) yes, or am I wrong?)
I think the losses are okay, because those peaks are so damn short - but I'm not sure...
One last question (I know, i asked to much
) is about the output LC filter.
I would like to use X7R or X5R caps instead of polycarbonate foil caps (cheaper, smaller, easy to get, surface mount,more types,...). To reduce the peak current, I would use more smaller values in parallel instead of one huge on. I know, for an Class A or AB ceramic caps are not suitable, but for Class D? Is this decision okay (especially in consideration of the switching frequency) - any advices?
Sorry for my worse English slang and for my (maybe) stupid questions. I never designed such power stages before. Usually I design FPGA Layouts...
Thanks for your help
Greetings from Germany