SMPS can be quite nimble; the fundamental limitation is the output filter network.
I don't see it's any problem for a "lab supply", as most of those have some big stinking 470uF or whatever on the output (seemingly, whether the control circuit / amplifier needs it or not), and that sets the transient short-circuit current (CV to CC transition), or recovery time / slew rate (CC to CV).
If the total capacitance of the filter is less than a typical linear unit's, then it's all up to the controls.
The impedance also matters:
Suppose the SMPS is a buck type with fixed duty cycle (freeze the control loop, for the thought experiment). Suppose it's also in forced CCM (synchronous inverter). The LC filter hanging off the inverter, has a Thevenin short-circuit at its input port (the inverter has very low impedance), the inverter ripple can be ignored for purposes of output dynamics (superposition applies), and the inverter can be seen as a Thevenin DC source proportional to inverter supply voltage times duty cycle. (You would almost always have inverter switch Rds(on) << filter Zo, so that the short-circuit condition applies.)
Given this setup: the series inductor is shorted to AC ground on one side, and the shunt capacitor is already to ground, therefore we draw an output-referred equivalent circuit, where the filter is a parallel resonant tank to ground, with characteristic impedance Zo = sqrt(L/C) and resonant frequency Fo = 1 / (2 pi sqrt(LC)).
If we apply a step current load to this tank, we get a corresponding ringing waveform, with peak voltage Vpk = Ipk Zo. The peak appears 1/4 wave or 1/(4 Fo) after the step, and repeats (+/-) thereafter.
Preferably, we would dampen this resonance so that repetitive current pulses, or generally frequencies near Fo, do not cause resonant gain. The capacitor should probably be electrolytic with ESR = Zo, in which case the peak voltage increases as there is an immediate voltage step in response to the current step, Vstep = Istep * ESR, which adds with the ringing waveform. (The Vstep decays exponentially as it's shunted by the inductor.) We can also use an ideal C, and shunt it with a "bulk C" with some loss; the resulting L + (C1 || (R+C2)) circuit can have a Q factor below 1 when C2 > 3 C1 or so, and R = Zo.
Notice what's happened through this process: for an input step current, some maximum peak voltage change results. This describes the transient impedance of the power supply, the self-regulation (change in Vo from change in Io). (As opposed to source regulation, which would be Vo vs. change in Vin or Iin. Or as opposed to Vo vs. set point, which is the gain or transfer function of the control. It's important to understand there are at least these three variables determining actual instantaneous Vo, and a power supply must take account of all of them.)
If we want a power supply that's maximally stable (output voltage/current ripple being the "least surprising" at any given setting), given some range of CV and CC operation say zero to max in each parameter, then we should simply set Zo = V_CV / I_CC.
That only leaves one free parameter, the Fo of the filter, which is determined by Fsw and acceptable output ripple, and the control loop response. (Control loop dominant pole must be much less than Fo for a voltage-mode type control, but current mode can in fact be above. I would most likely choose average current mode control for a project like this.)
As for ripple and noise, high-frequency noise is easily handled by filtering and shielding. I say easily, of course it's easy for me to say so, but to be perfectly transparent, it takes many years to develop a complete understanding of how to do this, and this goes beyond the scope of this thread/post. More to say that -- a solution exists, and it can be made arbitrarily good, given no other restrictions (like size or cost).
Ripple is the harder case, as the lowest-frequency content (Fsw or potentially subharmonics) directly conflicts with the goal of control loop bandwidth (in V or I, or any combination thereof, say if you want to mimic some Zo, not just CC or CV -- which really are just the special cases Zo --> 0 or infty). The same is true of a linear supply's control of course, but which is limited by device characteristics (pass transistor and driver speed?) rather than a network hanging off it.
Ripple can be handled in many ways. For example, a phase interleaved converter can cancel it out, so that each stage is running at Fsw yet Fsw is nulled in the output, with the dominant peak pushed to Fsw*N (for N stages interleaved). A linear stage can be employed in series or shunt, to stabilize the output voltage, current or impedance, in ways that a passive network cannot do; including feedforward from Fsw to null the ripple. A post-reg stage can be used to optimize transient response, allowing fast current or voltage limiting for example.
Tim