Switcher Input Supply.

[kvresto]

Hi Everyone.

In my previous thread I got some great advice on filtering the output of a switcher.

I started to look at the input supply voltage to my 5V switcher, which in this case its 15V DC benchtop p/supply, and my cro probe revealed input voltage ripple of about 150+mVpp. There was this very ugly high frequency stuff on the input shown in the pics. As the input to the switcher will in the final cct also be the input into some other blocks I was a bit concerned.

My cct has a 100nF cap next to the input pin, then a Panasonic EEE-FK1V331P 330uF low ESR electrlytic cap a bit further out as well. I was able to get rid of this high frequency switching noise by also fitting a TDK C3225X7R1E106M250AC 10uF ceramic cap next to the 100nF, as shown in the pic and the Vin ripple with the 10uF is ~ say 80mVpp.

I then removed the 330uF and  fitted 2 other electrolytic caps to the input of the switcher to see the difference, and:

1) 220uF EEEFK1E221P ESR=160mOhm, Input Voltage Ripple=150mVpp
2)  120uF Panasonic 35SVPF120M OS-CON ESR=18mOhm, Input Voltage Ripple < 20mVpp

So my question is am I heading in the right direction by playing with input caps, and what else can I do or other method to achieve good input filtering?

Thanks to everyone for their great help so far.

Kvresto.

[Alex Eisenhut]

Careful you're not chasing ghosts, how are you probing this?

[kvresto]

I used a spring clip on the probes GND terminal, and probed at the base of the 330uF input cap, I've included a pic of my cct, I've made this up in my w/shop, so I've designed it to be assemble friendly.

In the space between D26 and Chf I've put in the 10uF ceramic.

kvresto

[moffy]

Careful you're not chasing ghosts, how are you probing this?

Very possible.
Surprising that a 10uF cap would have such an effect on multi megahertz noise, they're usually not that good at those frequencies. Normally you would go with some 0.01uF and 0.001uf ceramic caps for the higher frequencies. Also some ferrite beads/inductors in series with the input would help. But your pics seem to show that the 10uF works. Curious.

[kvresto]

Moffy, very possible that it worked, OR very possible I'm chasing ghosts?

[kjs]

some of these higher value ceramic capacitors are surprisingly good in suppressing high frequency. Yes, their series resonance is below but they have rather low impedance at higher frequencies. Depends on the ceramic material and construction.

[moffy]

some of these higher value ceramic capacitors are surprisingly good in suppressing high frequency. Yes, their series resonance is below but they have rather low impedance at higher frequencies. Depends on the ceramic material and construction.

The 10u is ceramic? Well I'm certainly behind the times! I feel old.

[T3sl4co1l]

Yes, that's a good place and a good value for capacitance, right at the regulator input.  The switching loop is also small.

The output filtering might not be as great, hard to say without a clear view of the bottom (can you take a screen shot with transparent layers active, or one for each side?).  But output has lower ripple as well, so it's not a big deal.

Indeed, you have a second filter choke on the output, which isn't where it's needed -- total in/out noise is now most likely dominant at the input.  You could try scratching into that long VIN trace (between the 'lytic and 10uF) and tacking an inductor over it, see what that does.

The switching loop is small, but there may be voltage drop across it (even along the more-or-less solid ground on the backside), which will give you some common mode between the input and output.  You can measure that simply by probing the one ground while grounded to the other (mind that the wires don't intercept fields from the inductors or traces along the way).  You can also observe conducted or radiated noise by grounding the probe to its tip and poking that at whatever grounds you like.

Tim

[kvresto]

The GND plane is not so solid here. There is a 5V track and a 3.3V track. In the final layout the 3.3V track will be a power plane, the 5V track will remain.

Indeed, you have a second filter choke on the output, which isn't where it's needed

Tim can you elaborate? Do you mean no LC filter on the output at all. kinda asking to spell it out:)

kvresto.

[kvresto]

You could try scratching into that long VIN trace (between the 'lytic and 10uF) and tacking an inductor over it, see what that does.

I have a spare 3uH and a 22uH somewhere around, what size do you think will probably have any effect?

[T3sl4co1l]

Eww-ww-w!  That ground will not suffice!

Tips:
1. Route signals/power on top if possible (preferred routing layer).  Only dip into the bottom layer if necessary (crossing under components, avoiding noisy areas, crossing under tracks, etc.).  This keeps the bottom ground as solid as possible.
2. You don't need those big blobs around the pins -- cut down the 3.3 and 5.0V pours (or fills or whatever they are), or just remove them entirely (the pads have more than enough annular ring to support the pins themselves).
3. Bleh, why is the 3.3V reg even all the way over there?  Madness!  Shove that thing right by the connector, no need to run two traces all the way across the board!
4. Cfilt is on the wrong side -- it should be referenced to the output pin.  You could shove over Cout and Lfilt a little to get the needed space, or shuffle things around a little so, like, Cout is left of L1, and L/Cfilt are where Lfilt-Cout are now.
5. You can afford to use way more vias.  Especially on U8, if it's going to need some thermal sinking.  These can be via-in-pad (but mind solder wicking / thieving), or placed around the periphery of its tab (tented or otherwise).  A via on the inside (under the pin, just above the pad) of U8 GND could be used.  I like to stack a few vias in a row near large components (like Cin and Cout, and U8 as mentioned), helps reduce the inter-layer impedance of those grounds.  And vias can just be placed kind of wherever to help better marry the ground fills (stitching).

Now... if you're planning on hand making this PCB, you probably do want to be stingy on vias, and that's OK.  (You probably want to avoid top side soldered pins, too.  The top and bottom blocks/fills/pours around your connectors seem to suggest you've already had this thought...)  If you're buying, it hardly makes a difference in cost, at least until you get into seriously dense patterns (like "uncommitted prototype area" breadboarding stuff!).

As for the choke, another Lfilt would probably do.  Make sure it's well damped, you don't want the switcher going cuckoo because you've accidentally made a (lower frequency) resonant tank on its input!  This usually suggests small values (<1uH?), not enough to affect much LC filtering of the switching ripple itself, but it goes a long way towards knocking down those high frequency squiggles.

Tim

[kvresto]

Tim I read what your saying, but something is lost in my translation/visualisation.

Cfilt is on the wrong side -- it should be referenced to the output pin

I can't see what you mean here, isn't the output the +ve side of Cout?

You could shove over Cout and Lfilt a little to get the needed space, or shuffle things around a little so, like, Cout is left of L1, and L/Cfilt are where Lfilt-Cout are now.

I'm not sure I can visualise what you mean. The way I see it this will increase the output switching loop as now the GND for Cout will be much longer.

[Niklas]

I think Tim wanted the output filter cap to be located just on the output connector, essentially meaning that the capacitor must be rotated 180 degrees. Also check the GND trace on the bottom layer for the output connector and which way it will take from the output electrolytic cap.

[DanielS]

The 10u is ceramic? Well I'm certainly behind the times! I feel old.

About 10 years ago, DigiKey made a mistake on one of my orders and shipped me a strip of 100x 10µF 1610 caps instead of 100x 1µF 0805 - the bag had two different stickers on it, one that matched the parts I had ordered while the other matched the parts actually inside the bag. Back then, the price on those 10µF multi-layer chip capacitors (MLCC) was $1 a pop for strips of 100, today they are down to $0.10 or so. 10µF ceramic caps have been around for a while.

[moffy]

The 10u is ceramic? Well I'm certainly behind the times! I feel old.

About 10 years ago, DigiKey made a mistake on one of my orders and shipped me a strip of 100x 10µF 1610 caps instead of 100x 1µF 0805 - the bag had two different stickers on it, one that matched the parts I had ordered while the other matched the parts actually inside the bag. Back then, the price on those 10µF multi-layer chip capacitors (MLCC) was $1 a pop for strips of 100, today they are down to $0.10 or so. 10µF ceramic caps have been around for a while.

Yeah, I haven't done much with surface mount so that answers the question. Really nice though to have 10uF ceramic, no more low value tanatalums or electrolytics needed. They were horrible!

[kvresto]

Well, I've final completed the power supply to my project, all comments welcome. Tim I think this is what you were referring to in your previous post with regard to C&Lfilt.

I've included a couple of pics for comment. One is the switchers output after the LC filter, but its from the proto board I made up in my lab, its pictured in an earlier post above. The Linear reg is a TLV1117LV, its not the actual one pictured in the pic, its one put together on vero board and strapped to the 5V switchers filtered output, (again on the same board in an earlier post above).

So I've notice the linear regs output ripple seems to be higher than the switchers, is this got something to do with the higher frq stuff coming out of the switcher?? OR perhaps the way I've trapped them together?

cheers all

[T3sl4co1l]

How is that higher?  Or did you mean higher frequency?

Looks like interleaved crosstalk, like bits of ripple voltage, and induced ripple current, and induced inductor voltage.  It could be passing through the device, could be inductively coupled into traces, could be probing technique, or common mode.  Like I said, the PCB is kind of discombobulated, so you're bound to get some combination of these.

Tim

[kvresto]

oh yeh here is my new design, how did I not see that!!!!!!???

[kvresto]

So, Tim what your saying is its ok, so far? perhaps inherent in its layout? if so what do you think of my updated design? now that I uploaded it.

[T3sl4co1l]

Transparent? Or top and bottom?

[kvresto]

Transparent, 4 layers, I'm getting this one made up, previous 2 layer version was for testing the power supply.

[T3sl4co1l]

No, I mean, I can't see anything on the layers, unless you provide separate layer views, or use transparent view mode..

Unless there's complicated stuff below this section, I don't see why 4 layer would be necessary?

Tim

[kvresto]

oh, how do I use transparent view mode (not too experienced with Altium as yet).

4 layers, because theres so much more going on below what I cropped, I really struggled to get a good solid GND to all of the critical areas, for me the work needed to move/juggle/dance, everything around was kinda intense. No sooner you moved one thing, well you know the story.

EDIT: what you see is actually the top and bottom layers, inner layers are transparent.

[T3sl4co1l]

As you get more used to the tools, and learn the ways of routing, you'll start seeing simpler things right away.  It's solving a puzzle.  Takes time and experience.

I don't believe more than 2 layers is ever necessary or useful around "casual" sized parts (SOICs, SOTs, 0805s..), even at high density.  And a lot of finer pitch (TSSOP, QFP, 0603) work, too.  High density, fine pitch, is definitely easier on 4.  Multilayer is critical for BGA fanouts, but they can be done in 4 layers, many times.

The main thing that 4 layers gets you is usefully low trace impedances.  On 2 layers, it's simply not possible to fanout more than a pair of LVDS channels (even to an SOIC), that's how wide the traces have to be.  On 4 layers, they're thin like anything else, and easily routed to TSSOP and BGA parts.

I've seen 6 layer boards chock full of SOIC and THT parts.  Not even a BGA in sight.  What were those people thinking?  I can't even imagine what I'd want to route on that many layers, not without a pile of high density BGAs to work with...  I don't recommend doing that, but I guess that's just to say, employers or customers won't necessarily balk at that, despite the added cost.  Some projects truly are "cost no object", and don't give a shit.


Transparency is either set on the layers dialog (L) (last tab), or with the default (drop box on the toolbar, or from the list on the left side in the L dialog).

I don't even remember if the 2D Transparent setting is default (Altium 9+?), or if I cooked it up long ago and have just kept propagating it through everything I touch...

Tim

[kvresto]

Tim, you kinda have talked me into taking another look at doing it in 2 layers, I know there is a lot of stuffing about , but here goes.

cheers
kvresto