As free_electron noted, this is all for ESD protection, and the usefulness will be entirely dependent on the layout. It looks like the ESD is being shunted right to ground. Unless this is physically arranged near a chassis tie point, then the ground IS the chassis, in which case it better be a beefy ground pour, or something with a large free capacitance in air, regardless if it's effective as an actual ground plane or not. In that case, also better to shunt to the Vcc rail as well, a more classic arrangement, so you're actually reducing potentials across the circuit, not just rearranging them.
Also, there is a good chance that, in the final setting, the ESD suppressors would be more helpful on the other side of the resistors. If the resistors are a higher impedance to the ESD spike than other nearby conductors, then those suppressors will never get a chance to do their job.
My suggestion to you is to not just copy their ESD baggage, since I'm guessing in this case it's more vestigial--like a human appendix--than useful. If you are creating a product, then you will have to come up with an ESD plan based on that product, which is really not too hard if you follow some simple rules, as free_electron alludes to.
Consider visiting a testing lab when they are checking ESD compliance. If you don't know what's coming, then you will get to look on in horror as a nice gentleman zaps your device with a range from voltages from 2kV up to 16 kV, depending on your product. On every design after that, your first thought, after what the device is supposed to do, will be how to enclose and protect it from such insults.
In this case, I'm not sure that L2 is there to isolate ESD spikes from the system ground; otherwise each input would also need to be protected. I suspect GND is intended the system GND, and UGND is supposed to be the uP chip GND, which is floated by L2 from the system GND in case of uP current surges. If so, that's a bad design for obvious reasons (if it's not so obvious: You don't want your chip ground--and therefore I/O levels--shifting up and down relative to the rest of the board). The more classic design would be to tie the uP to GND normally, and put the inductor between the Vcc pin and system Vcc, combined with a proper decoupling cap, to impede surges from making their way back to the system Vcc. However, a look at the full circuit and layout will give some idea what was actually intended.