Somebody/something is wrong, but it doesn't appear to be our O.P.
The .lib file has:
.SUBCKT CD74AC14 Y A VCC AGND
and the .asy has pins VCC as netlist order 3 in the top left corner and AGND as netlist order 4 in the bottom left corner, and V2 polarity is correct, so its hooked up correctly in O.P's test jig.
Short of reverse engineering a schematic from the .lib netlist, it isn't going to be easy to figure out.
One clue may be a line in the .lib's comment header:
* - Built using generic logic gate behavioral pspice model V2
LTspice is UC Berkeley SPICE 3 compatible, with its own extended syntax etc. SPICE 3 does *NOT* support mixed mode or digital simulation, however LTspice does, with its own proprietary digital device primitives.
PSPICE also supports mixed mode and digital simulation, but it does so very differently. Don't expect LTspice to run PSPICE digital models cleanly, if at all!