Digital signal

[gaminn]

Hi,
I have 24 MHz clock which I want to derive several digital signals from as you can see in the picture (attached).

I tried this: As the frequency of the derived signals is 12 MHz and 6 MHz, I divided original 24 MHz clock via D flip flops to 12 MHz and 6 MHz. Then I connected suitable signals (24, 12 and 6 MHz) to NOT and AND gates to combine them to create desired signals. In simulation software, this works nicely. However, in real world with real components this attitude won't work (at least I think so), as clock division (D flip flop) and gates introduced some delay in 12 MHz clock and even more delay in 6 MHz clock.

Can you please help?

[Siwastaja]

Google for "synchronous logic". Basically, you'd clock all the flipflops from the 24 MHz clock. Then, your different paths can have different delays, as long as it's below the period of the 24MHz clock (plus some margin).

[gaminn]

I see, thanks. What components would you use for the logic in my picture? Discrete components or programmable logic devices? I need power dissipation as low as possible.

[Siwastaja]

Smallest CPLD you can get with a 24MHz oscillator might be a compact solution. I have used Altera stuff. There is some learning curve if you are not familiar with programmable logic ICs.

Definitely doable with discrete logic, too.

[PA0PBZ]

Looks like a decimal counter (like eg 4017) and a handful of diodes can do the job.

[David Hess]

Or use the epitomic 74HC161 or 74HC163 type of 4-bit binary synchronous counter.  But if whatever you are trying to do requires synchronous phase aligned clocks, then I suspect you are going to get into trouble.

[rstofer]

In my view...

You should show the clock on your timing diagram.  I would want to KNOW that there aren't transitions occurring on different edges or somewhere in the middle.

Then I would look at 5 D flops.  This would be the register.  The Q signals are the outputs.  They are also the address bits of a very small EEPROM (or whatever) that took the current output state and set up the D inputs for the next transition.  I would need to know that there are no duplicate states.  If there are duplicate states, I would try plan B.

For plan B, I would have synchronous counter as the address bits for the EEPROM (or whatever).  I would code the EEPROM with the desired output pattern.  Since we are reading the EEPROM in a sequential manner, the outputs may not need to be registered.  If I wanted to achieve perfection, I would take the EEPROM output into 5 D flop inputs and clock the flops on every cycle.  In this way, the signals would all be registered but delayed from the clock by one clock period.  This probably doesn't matter.

Or I would just use a CPLD.  An FPGA would work but would be overkill.  Either way, the results would be perfect and elegant.

[Benta]

Not so fast.
This timing circuit is much trickier than meets the eye.

The problem is, that the signals in the 1st, 2nd and 4 th traces (below the clock trace) rely on the clock high time for gating.

IF you can say that the 24 MHz clock signal is fully symmetrical (=50% duty-cycle), then you can do something.

Two possibilities:

1: you can double your master clock frequency by feeding the original clock plus a delayed clock into an EXOR gate. This will give you 48 MHz, from which you can derive the desired timing pulses from counter/decode circuitry.

2: you can clock your counters directly from 24 MHz and additionally delay the clock signal (eg, by feeding it through a series of gates) before gating it with the counter outputs.

Either way, I repeat: if your clock signal is not symmetrical, you have no simple solution. A PLL-based frequency multiplier would then be necessary (no disaster, ON Semi and others have ICs for clock generation and multiplication).

Cheers.

[Siwastaja]

I did miss that, looking at it too quickly! So more info is needed. Most importantly right now, "I have 24MHz clock" -- does this mean you have an external requirement of using a 24MHz clock which you need to sync to, or do you just need the outputs you have drawn, and thought that 24MHz input clock would do the job easily? It doesn't - indeed, a 48MHz clock would be the required input to be able to use simple synchronous logic. So if possible, use a 48MHz oscillator to supply the synchronous logic, which may be, as have been stated, a small CPLD or discrete logic (you might want to check if PLA is still a thing in the 2000's, you could use that with a binary counter.

Or maybe some CPLDs would support synthesizing logic triggering to both edges, if the 24MHz input requirement is a must?

[Someone]

Smells like a coursework question

[Benta]

Smells like a coursework question

And?

[gaminn]

Thanks all for the info. Please give me some time to understand it.

24 MHz clock comes from oscillator so it should have 50% duty.

The project is not coursework, it is professional project which is about reading image from image sensor. However, I'm not good in discrete logic...

I'm trying to make scanner consisting of two CIS (contact image sensors). Theirs outputs are sampled using WM8213 analog frontend, the digital data are read by Cortex M4 MCU and then transferred via USB to PC.

The discrete logic is located mainly between WM8213 and Cortex M4

We can discuss whether Cortex M4 is suitable for this application, but I think so in case there is some discrete logic which helps Cortex M4 read data from AFE (1200B bursts at 24 MB/s once per milisecond).