So, you essentially need the 8 outputs to be selectable between ten different patterns:
H H H H H H H H (none selected)
H H H H H H H L
H H H H H H L H
H H H H H L H H
H H H H L H H H
H H H L H H H H
H H L H H H H H
H L H H H H H H
L H H H H H H H
L L L L L L L L (all selected)
What about multiple devices trying to drive MISO to different potentials when more than one device is selected? You may need to think more about the details here.
That said, I'd consider a serial to parallel latch instead, maybe 74'595 or similar like edavid above, and a dual NOR gate logic chip (perhaps a 74'2G02, or two SOT-23-6 configurable logic gates). In addition to the SPI SCLK, MOSI, and MISO pins, you'd only need a separate /CS pin for the '595. '595 DS = SPI MOSI, /MR tied high, /OE = 0 nor /CS = not /CS, STCP = /CS, and SHCP = /CS nor SCLK.
This way, when /CS is high, the latch outputs are enabled, and the data goes to the SPI device(s) selected by the latch state, and the '595 sees no changes in SHCP or STCP.
When /CS is pulled low, the latch outputs go tristate. (You might wish to use pull-up resistors on the device /CS lines, so they're not selected in this state.) The next 8 bits clocked out from MOSI in SPI mode 0 will load the '595 shift register. When the /CS goes high, the shift register is latched to the '595 output pins.
This way, you can send the same sequence to any set among the 8 devices. The only thing I'd be wary about would be the MISO line, and more than one device trying to drive it at the same time. Many '595 can handle basically whatever SPI frequencies you want to use, too.