RX clk UART in FPGA

[rakeshm55]

Hi,

 I have a 150Mhz clk available..... I am trying to implement a 10Mbps UART with configurable baud rates in an FPGA.....

I have to generate the following baud rates too  ..... 10Mbps, 5Mbps,3Mbps, 1.2mbps, 1mbps ---- normal 115.2kbps

How to select the receive sample clock??? 16X sampling calls for a high reference clock rate.....  How can i receive above baud rates with less than 1% error rate.....

working on 10X sampling its easy to generate rx sample clock for the above baud rates....... for 10Mbps (5x) rest 10x.....

Is it advisable to work on 10X??

Is there any other work around for the above frequencies??..... Please help

[AndyC_772]

Start by carefully working out what the the important figures are that you actually need to achieve. With a UART, what you need to do is ensure your clock is accurate enough so you're sampling at some valid point within each data bit.

You don't need to sample each bit many times, and you don't need to sample each bit exactly in the middle. Just ensure that, assuming you synchronise the sample point at the beginning of the start bit, you're still sampling at some point within the valid window by the time of the stop bit.

If you work out the worst case clock slip, I suspect you'll find that you don't need 1% accuracy. You can slip nearly half a bit in 10 bits.

If it helps, use one of the PLLs in the FPGA to generate some other, more convenient reference clock from the 150 MHz input. You should be able, for example, to get 80 MHz from 150 Mhz using a PLL, and then oversample the incoming data 8 times.

[zapta]

Changing the UART clock to change the baud rate is one degree of freedom you have with FPGA. A second degree of freedom is to change the counter limits within the UART (does not have to be the same for all baud rates). A third degree of freedom is to have non even bit period, spreading the ratio reminder across bits.

You have plenty of control when designing with FPGA.

[mikeselectricstuff]

You don't need anywhere near 16x clock for a UART. One simple trick is to reset your baudrate divider on the startbit edge to minimise any jitter when using a low ratio of clock to baudrate.
Note however that when doing high rates you need to keep a close eye on external sources of jitter etc. For any distance it would need to be differential (RS422/485 or LVDS).
Self-clocking codes like manchester may be more suitable at higher rates.