How does slew rate control work in a chip like the LT1533?

[Atomillo]

Hello!

In the process of building some low noise HV supplies I came across Jim William's AN118 and switching regulators with controlled transition times such as the LT1533 that reduce high frequency harmonic contents and thus output noise.

Now, both in the datasheet of the IC itself as well as in various app notes (like for instance AN70) it is mentioned that slew rate is controlled with feedback so that it is relatively independent of the characteristics of the transformer. But how does this work? From the datasheets, I came up with the following schematic.

Which seems to work decently!

Here the feedback loop esentially tries to equal the current provided by V3 and R1 to that of dVout/dt and C1. Capacitor C2 simply limits the bandwitdh of the op-amp and the driver BJTs to ensure stability so that it is slower than the MOSFET+inductor. Note however the controlled voltage supply B1 that inverts the output voltage: this is needed to have negative feedback.

If I understand the circuit correctly, this inverter should be much much faster than the rest of the system to avoid instability. This is my problem at the moment! Furthermore, it seems not a very elegant solution.

Does anyone know how Linear Technologies actually solved this problem? I very much suspect their solution is much more elegant and efficient than mine but at the moment I can't come up with something better.

Many thanks in advance!

[julian1]

I think Fig 1 of An118 (looks like an op-amp integrator) and your ltspice simulation - control gate drive slew.

While for lt1533, the datasheet has a block diagram (p6) which shows collector feedback going to the slew-control block.

So i think the slew control is done with voltage feedback from the collector/drain. Rather than the drive (base/fet).

 
The datasheet theory of operation (p7) indicates that it is controlling slew of *both* voltage (via collector) and current (internal currense-sense resistor under the emitters).

    Control of output voltage and current slew rates is done via
    two feedback loops. One loop controls the output switch
    collector voltage dV/dt and the other loop controls the
    emitter current dI/dt. Output slew control is achieved by
    comparing the currents generated by these two slewing
    events to currents created by external resistors RVSL and
    OPERATIOU
    RCSL. The two control loops are combined internally to
    provide a smooth transition from current slew control to
    voltage slew control

  https://au.mouser.com/datasheet/2/609/1533f-2954000.pdf

[Jay_Diddy_B]

Hi,
You can reduce that circuit to this:



The circuit is called a Miller integrator. During the time the voltage is slewing the current from the Drain Gate capacitor equals the current from the gate drive.

I have attached the model.

Jay_Diddy_B
 slew control.asc (1.79 kB - downloaded 42 times.)

[cellularmitosis]

Jay, what causes the shelf at 4 volts for the 10nF?

[Kleinstein]

The 4 V phase is the so called miller plateau. It is not only presenst with the 10 nF case - if is also found with just the MOSFET when the gate drive is relatively high impedance. It is just the voltage where the gate is in the active range. So relatively little change in the gate voltage is needed to get the targetted slew rate.

[Atomillo]

Hi,
You can reduce that circuit to this:



The circuit is called a Miller integrator. During the time the voltage is slewing the current from the Drain Gate capacitor equals the current from the gate drive.

I have attached the model.

Jay_Diddy_B
(Attachment Link)

Hello!

Many thanks for your help. Two questions arise:

If I understand it correctly, resistor R2 controls the fall time (when the MOSFET turns on) and then the rise time (when the MOSFET turns off) diode D2 conducts and the resultant resistor is R2 and R3 in parallel, which is why the rise time is a little bit faster than the fall time. Is this correct?

If I eliminate D2 and R3 completely, then I can see that fall times are much much slower than the rise times. Why is this so? Isn't then the capacitor charged and discharged through the same resistor and thus, shouldn't they be the same?

And finally, if such a simple circuit is sufficient, why bother with feedback? I've tried to think about it but I don't know if what I came up with makes sense: in this circuit, capacitor Cslew gets amplified by the gain of the MOSFET (the Miller effect). However this gain depends on it's load, thus, in order to achieve repeatable slew rates one would need to adapt the resistors and such to every case. Is this correct?

Once again many thanks for your help!

[Atomillo]

I think Fig 1 of An118 (looks like an op-amp integrator) and your ltspice simulation - control gate drive slew.

While for lt1533, the datasheet has a block diagram (p6) which shows collector feedback going to the slew-control block.

So i think the slew control is done with voltage feedback from the collector/drain. Rather than the drive (base/fet).

 
The datasheet theory of operation (p7) indicates that it is controlling slew of *both* voltage (via collector) and current (internal currense-sense resistor under the emitters).

    Control of output voltage and current slew rates is done via
    two feedback loops. One loop controls the output switch
    collector voltage dV/dt and the other loop controls the
    emitter current dI/dt. Output slew control is achieved by
    comparing the currents generated by these two slewing
    events to currents created by external resistors RVSL and
    OPERATIOU
    RCSL. The two control loops are combined internally to
    provide a smooth transition from current slew control to
    voltage slew control

  https://au.mouser.com/datasheet/2/609/1533f-2954000.pdf

I now understand why they do it in separate feedback loops I think. The current can be relatively easily measured by inserting a resistor in the emitter of the switching resistor (and thus will be in phase with the original signal; more control base signal more current) while the voltage would be measured in the collector and would thus be in antiphase (more control base signal less voltage). Thus it makes sense to separate both, and it also allows separate control.

[Atomillo]

I've also made a new circuit.

And discovered what is the cause for instability when the rise/fall times are set too low (which is just when you would expect the thing to be stable!). Consider the diagram without the Schottky diodes D2 and D3 and without capacitor C2. The op-amp is saturated when the MOSFET is fully switched on/off, thus the virtual ground does not apply and the non-inverting terminal is at some large voltage.

When the time to change states comes, the op-amp must first get out of saturation. However in order to do this it must decrease the voltage at the non-inverting terminal. If we take too long to do this, then I believe we end up in a situation of "integral windup": the op-amp sees a very large error and overcompensates, which of course cause an error in the oposite direction, which also tries to correct, etc...

The result is the first simulation shown: oscillation at low slew rates (when the acumulated error is largest)!! (Vn003 is the voltage at the non inverting input and Vn004 the voltage at the output of the op-amp).

If now we add the diodes the result is much much better but at the slowest slew rate oscillation still occurs, because the accumulated error is much to large and the op-amp reacts to it very fast.

Finally adding capacitor C2 makes it so that the response is slower and eliminates all oscilations.

Of course Linear must have taken this account or even better, a way to avoid saturation when the output is switched on/off.

However a Miller integrator like that shown by Jay seems to perform identically and is much much better. So for something that isn't an integrated solution feedback solutions might just not make sense.

[Kleinstein]

The D2 R3 part is to increase the slew rate for the FET turn on part. In more normal cases the diode D2 would be the other way around. Without the extra trim one can get some asymmetry depending on the drive amplitude relative to the gate voltage treshold. So instead of D2 and R3 one could as well adjust the drive amplitude.

[Jay_Diddy_B]

Hi,

Kleinstein has the correct answer, it is to make the dv/dt symmetrical.

Consider this:



Assuming the gate drive voltage is symmetrical, +/- 10V was used in the example, the gate threshold voltage results in asymmetric dv/dt. By 'changing' the resistor, using a diode as a switch, the dv/dt can be symmetrical for turn-on and turn-off.

Regards,

Jay_Diddy_B

[Atomillo]

Many thanks!!
It now makes a lot more sense.
And this simple circuit makes everything a lot easier.