Author Topic: SPI EEPROM - polling status register for WIP/RDY  (Read 979 times)

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Online HwAoRrDkTopic starter

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SPI EEPROM - polling status register for WIP/RDY
« on: June 12, 2019, 12:04:07 am »
I'm currently writing some MCU code that interfaces with an external SPI EEPROM, but am unsure whether a method I would like to use is widely supported by all EEPROM manufacturers.

Using the RDSR command, the status register can be read to determine whether there is a write still in progress by looking at the WIP (a.k.a. RDY) bit. The datasheet for the particular EEPROM chip I'm using from ST (an M95256) says that the status register can be repeatedly read by continually clocking bytes out - that is, you can continuously read the status over-and-over as many times as you like in one SPI transaction.

Does anyone know whether EEPROMs from other manufacturers support this method of polling the status register? I have looked at datasheets for equivalent chips from Microchip (25AA256), Atmel (AT25256B) and ON Semi (CAT25256), but I can't see any explicit mention of whether this is supported. :-//
 

Offline HB9EVI

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Re: SPI EEPROM - polling status register for WIP/RDY
« Reply #1 on: June 12, 2019, 08:28:57 am »
afaik from my few projects using SPI eeproms (25LC640) it's the same; I didn't check now if bit positions are the same, but at least all is named the same way.
 

Online HwAoRrDkTopic starter

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Re: SPI EEPROM - polling status register for WIP/RDY
« Reply #2 on: June 12, 2019, 03:29:29 pm »
Yes, the bit positions and meaning all seem to be standard; I have no concern there. Just whether continuous clocking out of the status register is supported by all manufacturers.

Wish I had the foresight to buy a variety of parts from various manufacturers so I could test for myself.
 

Online HwAoRrDkTopic starter

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Re: SPI EEPROM - polling status register for WIP/RDY
« Reply #3 on: June 12, 2019, 04:56:46 pm »
I have been reading some app notes from various manufacturers (Microchip, Atmel, ISSI) and they all implicitly show - in flow diagrams or example code - a full SPI transaction cycle (toggling CS, issuing RDSR command, etc) for polling the status register.

This seems... needlessly inefficient. Surely it can't be just ST EEPROMs that facilitate polling by continuous clocking, can it?
 

Online HwAoRrDkTopic starter

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Re: SPI EEPROM - polling status register for WIP/RDY
« Reply #4 on: June 12, 2019, 06:40:33 pm »
Well, I think I found my own answer. In ST application note AN2014, they state:

Quote
For compatibility reasons, it is recommended to send the full RDSR command each time instead of continuously reading the status register.

So, one must conclude that the latter behaviour is not supported by many (or all) other manufacturers.

It would be nice if other manufacturers explicitly said so in their datasheets or app notes, but they don't. >:(
 


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