Rate this discrete gate driver circuit

[Dabbot]

A discrete gate driver circuit I came up with while working on something else. I did consider the usual suspects but there were no real constraints for this.


Pros:
- Rail to rail
- Configurable rise and fall times via R4 and R5 gate resistors
- Configurable logic level via R1 and R2
- Separate logic and gate drive supplies
- Inverting (pictured) and non-inverting (swap Q1 Q2 common-base and common-emitter connections)

Cons:
- Discrete and probably slow (<1uS from measurements on the breadboard)
- Shoot-through (Mitigated by R4 and R5. Can be further mitigated with baker clamping on Q3 and Q4)
- A bit partsy (Jellybean parts though)


Edit: Added b-e resistors to Q3 and Q4

[magic]

I had a similar idea, but also tie Q1 and Q2 bases together to reduce shoot-through. They could be biased to VCC/2 or driven by another GPIO. If the latter, two GPIOs should switch in anti-phase. Setting them equal makes the driver output hi-Z - not a great idea for gates, though maybe useful for other applications.

[Zero999]

Q4 & Q4 could do with base-emitter resistors.

[MarkT]

Well its got stored-charge issues and Miller effect slowing it down.  This is why FETs make a good choice for gate drivers being capable of snappy switching and and switch off as fast as they switch on.  But why not just choose a suitable MOSFET or IGBT drive chip.

100 ohms is very high output resistance to drive a big MOSFET, again slow...  Checkout my fave driver chip, MIC4422 (inverting version MIC4421) for what you are competing with.

[boz]

What voltages are we talking about ?

[xavier60]

ST has a family of Gate drivers that might be useful to know about. Ill likely never use anything else.
This part has the option of separate outputs or single plus Miller clamp.
https://www.st.com/resource/en/datasheet/stgap2hs.pdf SO-8Wide

Edit: beware of parts that are intended for driving SiC MOSFETs which can have UVLO voltage which is too high for Si MOSFETs.
SO-8 version https://au.mouser.com/datasheet/2/389/stgap2s-1499130.pdf

[Dabbot]

I had a similar idea, but also tie Q1 and Q2 bases together to reduce shoot-through. They could be biased to VCC/2 or driven by another GPIO.

In the schematic they are tied together and biased at half the logic supply.

If the latter, two GPIOs should switch in anti-phase. Setting them equal makes the driver output hi-Z - not a great idea for gates, though maybe useful for other applications.

I might give this a try. I'll just have to be careful not to reverse-bias Q1 and Q2 b-e junctions too far.

Q4 & Q4 could do with base-emitter resistors.

Oops. I missed that. Thanks!

What voltages are we talking about ?

12V gate drive, 5V logic.

Well its got stored-charge issues and Miller effect slowing it down.  This is why FETs make a good choice for gate drivers being capable of snappy switching and and switch off as fast as they switch on.  But why not just choose a suitable MOSFET or IGBT drive chip.

100 ohms is very high output resistance to drive a big MOSFET, again slow...  Checkout my fave driver chip, MIC4422 (inverting version MIC4421) for what you are competing with.

ST has a family of Gate drivers that might be useful to know about. Ill likely never use anything else.
This part has the option of separate outputs or single plus Miller clamp.
https://www.st.com/resource/en/datasheet/stgap2hs.pdf

I do have some gate drivers on hand. Both of those are some very nice options. Noted for my next digikey buy.
This application wasn't very demanding speed-wise, so I tried a discrete approach.

[xavier60]

I have added an important edit to Reply #5.

[T3sl4co1l]

You might find this of interest:
https://www.seventransistorlabs.com/Images/Diode_Recovery_Tester.pdf

I later added a complementary emitter follower output anyway, which somewhat obviates the slope control due to its current gain, to get moderately-fast dI/dt out of a moderately sized (ballpark 600V 20A) transistor.  A little Miller capacitance (from follower output to driver base) could be used to control gate dV/dt again, and thus drain dI/dt to an extent.

Typical current rates are on the order of 500A/us:



That's 5A/div and 20V/div.  DSEP29-06A, If = 10A, t_rr ~ 44ns, dI/dt ~ 500 A/us (kinda has two slopes either because of uncompensated stray inductance in the shunt, source inductance, or transistor characteristics), Irr ~ 13A.  Which I think was using a STP19NM50N for the switch.

Tim

[Zero999]

I posted a similar circuit here a few years ago. It doesn't have the output resistors, which are a good idea.


https://www.eevblog.com/forum/beginners/op-amp-as-buffer-not-behaving-as-expected/msg1535255/#msg1535255

[Dabbot]

You might find this of interest:
https://www.seventransistorlabs.com/Images/Diode_Recovery_Tester.pdf

I'm looking at D6 and D13 amongst the b-e resistors. Keeping the drivers out of saturation?

[T3sl4co1l]

Crude Vbe compensation: they're current sources.

Tim

[Dabbot]

Crude Vbe compensation: they're current sources.

Tim

I see it now.