Hi, the schematic looks better now, but it can still be cleaned up a bit. E g the placement of C8 is miserable. Messy schematics have a strong tendency to go along with stupid misses like the missing ref supply before. Or connecting the Vref supply to a
single pin net...
So get it right. Including defining all refdes. NC crosses (or similar) on deliberately open pins is also recommended.
You get credit for the protection diodes
Using schottky diodes instead might be considered.
Connect U1 sleep pin to its supply pin (optionally via a pull up R) - but that was your intention of course
Depending on your board (2 or 4 layer?) and layout , you might need a small cap at U1 supply pin as well.
If you're going into this business, you might start adding a pull-down/pull-up resistor on enable pins right now. In real life, i.e. in production tests the manufacturer wants to be able to disable anythin that can be disabled. While your at it, you could add a pullup on the reset and PDWN pins as well.
Regarding the noise coupling, the noise that couples through IC3 will couple through IC1 as well...what you need is a ferrite bead. The question then is where to put it. With a 4-layer board, I'd put it between IC3 output (with a minimum cap) and the decoupling caps for ADS1255, make a local plane for DVDD.
A series resistor on the oscillator output is generally needed to trim the drive level of the crystal. Sometimes a parallel R across XIN/XOUT is a good feature, but sometimes it's included on the chip.
BR,
Carl