The goal of this project is to implement an Altera MAX 10 FPGA into a small board with headers to use it is a digital pattern generator to exercise other circuits. It will have 32 outputs, well, because that is what I decided on. It will be controlled from a desktop app via USB. The MAX 10 part is a 3.3V part, to allow for 5V outputs I am using 75HCT541 buffers to do the 5V translation. Regulation via AMS1117-5.0 and AMS1117-3.3, 7V input. To keep the USB simple I am using a MPC2200 which is USB-to-GPIO. I plan to simply clock data into the FPGA. I don't want to use a USB-to-UART IC because then I am looking at some sort of UART state machine which I can't visualize as easily as a shift register. In general, the whole design is made to be similar to Altera's reference design with respect to the JTAG, bypass capacitors, clock design, reset circuit design, etc. The differences is that I am hanging the MCP2200 and four 75HCT541s off that design and using cheap linear regulators that I already have. At least that is the idea.
Hopefully, my PCB layout doesn't suck. This is the most complex design I have done by hand. No auto-routing this time. I try to run similar signals together and with the same trace lengths. Four layers, top and bottom are signal, one ground, and one is split between 3.3V and 5.0V, with 5.0V running under the buffers as they are the only part that runs at 5.0V. Take a look at how I split that and run the output of my 5.0V regulator to it. Is that split copper pour and how I run the trace to 5.0V sane or not? Overall, is the design OK, sane, or could I do better? How is my decoupling situation around the FPGA, regulators, and buffers?
Attached is what I think you need to see plus Altera's reference design. Thanks!
Notes to self so far: Need silk-screen for the output section. Need to make my 3V3 via from the regulator to the copper pour on the inner layer bigger, at least as big as the one I did for 5V0.
https://www.eevblog.com/forum/projects/please-comment-on-my-schematic-and-pcb-layout-for-this-small-fpga-project/?action=dlattach;attach=301808