Easy DIY 5.5 Digit DVM + Volt Ref./Cal. (LTC2400+LTC6655 / SPI uC / Arduino)

[iMo]

With your LD120 you would need something like this (that figure 7 shows how to bypass the internal crappy opamp in the LD120)..
So a small board with a DG switch and the opamp, and do redirect pins 15 and 1 on the LD120 to your new board, and wire the M/Z signal from the LD121A..

[David Hess]

That is the plan.  The hard part was finding a suitable operational amplifier and analog switch.  It helped that there was the Tektronix reference design with the AD542, so I had some idea of what was required.  I finally got the DG419 for the switch but wish I could have found something with lower specified leakage.  The problem here was actually finding DG419's in stock.

I guess if you want lower leakage, then a discrete solution for the multiplexer is required, but I was not willing to go that far initially, and a search does not show any FETs which are better anyway.  First I will see how the DG419 works out.

[Kleinstein]

The DG419 is a rather low resistance switch. There could be lower leakage ones with higher resistance. Even a slected 4053 could be an option, if the voltage range is sufficient. The specs are loose, but actual performance often not that bad. Today there are plenty of CMOS switches to choose from. A TMUX6119 would be a modern candidate with low leakage. Compared to this discrete JFETs are rarely wirth the extra effort.

It is not only the leakage that can be an issue, but also the switching spike (the off part is the charge injection but the turn on part can be the more troublesome).

[iMo]

LD120/121A is a 4.5digits voltmeter only, so the DG419 with its <+/-0.75nA @25C leakage may work fine. With modern opamps and switches and its multislope, with perhaps a 12bit ADC for reading the residual charge the LD120/121A concept will work 6 digits, my bet.. But that is an another story..

[David Hess]

The DG419 is a rather low resistance switch. There could be lower leakage ones with higher resistance. Even a slected 4053 could be an option, if the voltage range is sufficient. The specs are loose, but actual performance often not that bad. Today there are plenty of CMOS switches to choose from. A TMUX6119 would be a modern candidate with low leakage. Compared to this discrete JFETs are rarely wirth the extra effort.

Of the ones I checked, the DG419 was about the best option.  I will try the TMUX6119 if the DG419 does not work out because I am not interested in buying a bunch of DG419s and grading them.

It is not only the leakage that can be an issue, but also the switching spike (the off part is the charge injection but the turn on part can be the more troublesome).

That is something I will just have to test for.

LD120/121A is a 4.5digits voltmeter only, so the DG419 with its <+/-0.75nA @25C leakage may work fine.

The series protection is 500 kilohms, which is pretty typical, so input bias and leakage current yield an error of 20 picoamps per count.

Better performance might actually be available by using an OPA140 as a buffer *before* the multiplexer if its offset could be nulled out, but only because the OPA140 has such good DC precision.

With modern opamps and switches and its multislope, with perhaps a 12bit ADC for reading the residual charge the LD120/121A concept will work 6 digits, my bet.. But that is an another story.

That might be the case since HP got that kind of performance out of their similar run-up/run-down converters.  Integrating dual-slope converters sure cannot achieve that.  Thinking about it now, I wonder why nobody ever implemented an integrating run-up/run-down converter with charge injection compensation as a generally available ASIC.  Maybe someone did, but I missed it.

[iMo]

..Thinking about it now, I wonder why nobody ever implemented an integrating run-up/run-down converter with charge injection compensation as a generally available ASIC..

Shit happens.. 
PS: Moreover the LD12x is 44y old design with none supporting MCU (none supporting math!).
Imagine the RP2040 with the PIO state machines with the improved LD122, and with math for gain, offset, temperature, linearity compensation implemented.. Would be a nice project (and an attempt with LD120 as the template was done by "NNNI" occasional poster, afaik)..
https://hackaday.io/project/190528/logs

[Kleinstein]

With modern opamps and switches and its multislope, with perhaps a 12bit ADC for reading the residual charge the LD120/121A concept will work 6 digits, my bet.. But that is an another story.

That might be the case since HP got that kind of performance out of their similar run-up/run-down converters.  Integrating dual-slope converters sure cannot achieve that.  Thinking about it now, I wonder why nobody ever implemented an integrating run-up/run-down converter with charge injection compensation as a generally available ASIC.  Maybe someone did, but I missed it.

The LD120 type run-up and an ADC (10 bit) reading the residual charge is about how the multi-slope 3 ADC in the HP34401 works.
It still needs more care with the integrator and clock to get really low noise.

Integrating the ADC to a single chips was a bit tricky, as it includes digital and demanding analog parts that were not easy to make with the same process. At the time one would have wanted CMOS or PMOS for the logic, BJT based for the reference part and JFETs for the Integrator and input buffer.  There are a few chips for 4.5 digit dual slope and related with run-down variations, but AFAIK the LD120 is the only type with a multi-slope type run-up. The compensation for the charge injection (using the fast mudulation for the zero phase) was needed for a direct display version. It is no longer needed with a digital offset compensation / auto zero.

The classic MS ADCs used a CPU / µC for the control.  With a modern µC this can still be build relatively simple. The modern SD Chips are however still simpler, even though for high performance one also needs quite some drivers for the inputs and reference. So it is often not just the ADC chip (except for the ADS125H , that even includes an input amplifier and is fast enough for reasonable BW digital RMS).

[iMo]

The ADS125H02 at +/-13.3V input and 2.5smps and 2.5 Vref shows (DS) 0.6-0.89uVrms noise, that is better than the 34401A, imho. Not sure about other params, but definitely worth of consideration..

[Kleinstein]

The noise performance of the ADS125H is good. However the INL and gain stability is not that good. With a 2.5-3 V reference one is likely not planing with a LM399 or similar reference and the Bandgap type reference chips tend to be not as stable anyway. It would not consider it worth dividing down a 7 V ref, with the ADC gain not that stable anyway.
It would still be a pretty simple way to get to the 5.5 digit or low end 6 digit range. The limiting part is more the INL and gain drift, not the noise. So it could be a pretty fast (e.g. 50/60 SPS) 5.5. digit meter.
Another limiting factor is the input current:  some 100-500 pA is a bit on the high side to directly use it for the input. So one may still want and extra buffer at the input for a lower bias input.

[NNNI]

Imagine the RP2040 with the PIO state machines with the improved LD122, and with math for gain, offset, temperature, linearity compensation implemented.. Would be a nice project (and an attempt with LD120 as the template was done by "NNNI" occasional poster, afaik)..

My design was not based on the LD120/121 chipset (I discovered them after I started working on mine) but instead the basic outline in The Art of Electronics 3rd Edition.

When I started the project, I barely had any experience working with microcontrollers, having only dealt with the Arduino framework and some very basic STM32 + CubeIDE projects. I was then introduced to the Raspberry Pi Pico, with its on board RP2040. The PIO peripheral ended up being the saving grace of the multislope project. The RP2040 already seems to have been dismissed as a toy on this forum (https://www.eevblog.com/forum/projects/thoughts-on-the-rp2040/). Although its peripherals might not be as numerous or mature as the ones on, say, an STM32 microcontroller, the C/C++ SDK and documentation are excellent and quite accessible even to beginners. With a little bit of creativity, the PIO peripheral is quite powerful in the things it can implement. I like to say: one can only think out of the box if there is a box (in this case, limitations) in the first place.

I haven't found much time to work on my multislope project in the last few months. However, I plan to clear up my backlog of other projects soon and devote time to finishing and perfecting the design. Of course, I will be posting the results on Hackaday and here (I recollect creating a separate thread last year).

Edit: If using an integrated ADC IC is preferred, the RP2040 PIO can also help with that...I used it to talk to an AD5791 DAC. It should be possible to quite easily talk to ADCs (or anything, for that matter) that have a weird interface.

[iMo]

..Another limiting factor is the input current:  some 100-500 pA is a bit on the high side to directly use it for the input. So one may still want and extra buffer at the input for a lower bias input.

A high time to develop a small easy to use "AFE Module" for all modern SAR/SD ADCs.
A small pcb, with bootstrapped opamps, input protection and the divider.
The Vcc/Vee say +/-60V max, thus the input say +/-50V, >10Gohm.

We have to ask TiN to recall a new design competition! Will Jaromir win again??
 

[Kleinstein]

Getting high voltage like +-50 V with high impedance is already quite special, more like the electrometer range. For the most part this is not really a challange.

The modern SD/SAR chips are similar at the inputs, but still not all the same.
E.g. the ADS1259, as one candidate supports an extra negative supply for the analog part, that can simplifiy things a little, but would make it incompatible with many other parts.
There are also types for a more +-2.5 V range and +-5 V range.
Another complication for a universal front end is the need for compromises (noise, bias, INL, costs, power, maximum voltage), that depend on the use case and ADC.

For a more normal SD ADC I would consider a front end similar to the Sigilent SDM3065, but starting with a 2.5 - 5 V reference. From crude reverse engeniering this look like it uses a driven low side / common terminal to get a 20 V range with high impedance with still only a +-15 V supply. The sequence is than like amplifier (or maybe just a buffer), switchable dividers, buffers , ADC. It does not look like it uses a bootstrapped supply though. One could use bootstrapping for the input amplifier, but it complicates the stability. For the lower end 6 digit range a single good OP-amp could be still be good enough.
Boostrapping may be more a thing to use a 5 V AZ amplifier.

When starting with a 7 V reference, I would still prefer the µC controlled multi-slope way. It simplifies the front end by starting with a +-10-12 V input range (and thus litte need for a divider stage in between) and easy drive. Once the support circuit for the SD ADC chip is included, the effort gets more comparable.

[iMo]

..For the lower end 6 digit range a single good OP-amp could be still be good enough.

For 6 digits like
LTC2057HV up to say +/-25V input (+/-30V max supply range)
OPA189, OPA140, LTC2057 input max +/-15V (+/-18V max supply range)?

[David Hess]

Integrating the ADC to a single chips was a bit tricky, as it includes digital and demanding analog parts that were not easy to make with the same process. At the time one would have wanted CMOS or PMOS for the logic, BJT based for the reference part and JFETs for the Integrator and input buffer.  There are a few chips for 4.5 digit dual slope and related with run-down variations, but AFAIK the LD120 is the only type with a multi-slope type run-up. The compensation for the charge injection (using the fast mudulation for the zero phase) was needed for a direct display version. It is no longer needed with a digital offset compensation / auto zero.

The classic MS ADCs used a CPU / µC for the control.  With a modern µC this can still be build relatively simple. The modern SD Chips are however still simpler, even though for high performance one also needs quite some drivers for the inputs and reference. So it is often not just the ADC chip (except for the ADS125H , that even includes an input amplifier and is fast enough for reasonable BW digital RMS).

What I was getting at is that it would be a small step to modify the digital control section of the LD120/LD121 to implement charge injection compensation like HP did where a constant number of switching actions occur so the charge injection error is constant and can be treated as offset.  I assume they did not think of it or other errors dominated, which would have been the case anyway with the LD120's internal buffer or any likely external buffer on the LD122.

[dobsonr741]

A high time to develop a small easy to use "AFE Module" for all modern SAR/SD ADCs.
A small pcb, with bootstrapped opamps, input protection and the divider.

How about this one? https://www.analog.com/en/products/ada4255.html

I am buddying it up with an LTC2440, in progress for a while.

[iMo]

Integrating the ADC to a single chips was a bit tricky, as it includes digital and demanding analog parts that were not easy to make with the same process. At the time one would have wanted CMOS or PMOS for the logic, BJT based for the reference part and JFETs for the Integrator and input buffer.  There are a few chips for 4.5 digit dual slope and related with run-down variations, but AFAIK the LD120 is the only type with a multi-slope type run-up. The compensation for the charge injection (using the fast mudulation for the zero phase) was needed for a direct display version. It is no longer needed with a digital offset compensation / auto zero.

The classic MS ADCs used a CPU / µC for the control.  With a modern µC this can still be build relatively simple. The modern SD Chips are however still simpler, even though for high performance one also needs quite some drivers for the inputs and reference. So it is often not just the ADC chip (except for the ADS125H , that even includes an input amplifier and is fast enough for reasonable BW digital RMS).

What I was getting at is that it would be a small step to modify the digital control section of the LD120/LD121 to implement charge injection compensation like HP did where a constant number of switching actions occur so the charge injection error is constant and can be treated as offset.  I assume they did not think of it or other errors dominated, which would have been the case anyway with the LD120's internal buffer or any likely external buffer on the LD122.

LD120/121A does the charge injection compensation - see the small zig-zags at the multislope peaks..

[iMo]

A high time to develop a small easy to use "AFE Module" for all modern SAR/SD ADCs.
A small pcb, with bootstrapped opamps, input protection and the divider.

How about this one? https://www.analog.com/en/products/ada4255.html

I am buddying it up with an LTC2440, in progress for a while.

That is a cool chip, indeed, what is less impressive (at a first glance) is its noise - ie with gain 1/16V / V it is 100uVpp, with 1V/V 6uVpp, so at something close to +/-10V input range (1/4V /V) I would estimate 25uVpp (but perhaps I am mistaken somehow)..
That leads to max 5.5digits, perhaps (what is ok considering the subject of this thread).. Not sure with other params, however..

[David Hess]

LD120/121A does the charge injection compensation - see the small zig-zags at the multislope peaks..

I think there is more to it than that; there has to be the same number of switch cycles on every integration so that the same amount of charge is transferred.  HP published an application note about it.

[Kleinstein]

The way the LD120 works, it has the same number of switching events for each integration.  The small zig zags make shure to have the same switching sequence. The HP34401 still uses essentially the same pattern. The control is simple, but still quite good. Even a not perfect settling of the reference buffer or integrator in the short phases is not such a problem: the number of the short pulses is linear in the input signal and the settling errors thus don't add up to an INL contribution.

Even the zero phase gets a somewhat similar rate of switching events and thus a reasonable good zero.
It looks more that the quality of the amplifiers inside the LD120 is somewhat limiting, not the control logic ( LD121).

A downside of the LD120 is that the resistors (R1 and R2) effect the ADC gain and thus should be low TC, low drift ones.
At least the Datasheet version that I have is odd in suggesting a mica capacitor for the integrator. The obvious choices are PS, PP or C0G ceramic (was hardly available in ~ 1 nF size when the chip was new).

[iMo]

You may easily download the "1982 Siliconix Analog Switch and IC Product Data Book" (24MB) where there is about 100pages dedicated to the 120/122. There are design notes for the external opamp/switch as well. They claim 1uV resolution at 20mV FS with the 122.

When you download the Siliconix 1982 data book you may find there an elaborate list of hints in various app notes how to handle the construction of the LD120/122 based meters. There is basically everything we know today as the best practices for uV and sub uV designs (EMF, noise, grounding, leakages, DA, etc).
There is an Appendix A with "Error terms" math.
Regarding the resistors and capacitors in LD120/122 - around the page 7-75 there is following (and more) - see below.
For example they mention the ratio TC of the R1 and R2 should be equal or smaller than the 10ppm/C recommended for the voltage reference with 4.5 digits.

[iMo]

LD120/121A does the charge injection compensation - see the small zig-zags at the multislope peaks..

I think there is more to it than that; there has to be the same number of switch cycles on every integration so that the same amount of charge is transferred.  HP published an application note about it.

Not sure we have to discuss the LD120/122 in this thread (it is about LTC2400) - but when you are improving your multimeters - here is an another thing worth to have a look - the offset compensation of the LD120/122 as seen in the app notes with a small 200pF capacitor and the 100k trimmer.

Moreover  - I've spent some time reading the US patent US-4164733-A by Landsburg; George F. et al. (Siliconix) published in 1979 on the improvement of the LD120/LD122/LD121.

Interestingly, the patent describes an improvement where the AZ capacitor is connected to the "virtual ground" (the pin 9 - input of the integrator) instead to "ground" and the inv input of the comparator is wired to ground instead to output of the AZ amplifier (as has been depicted in all datasheets and app notes). In addition, the patent describes a split of the AZ phase into two parts AZ1 and AZ2, utilizing the different wiring of the AZ capacitor and comparator.
The patent claimed a significant improvement (see the patent).

It looks like Siliconix decided not to improve the silicon (in both chips) based on its own patent (filed in 1977, btw.).

PS: Or, perhaps all the datasheets lie? 
Would be great to look at the actual signals with an oscope

[jorgemef]

Hello,
I went and checked in AD forum someone complaining from noise from SPI lines and the AD expert suggested that was no SPI noise and for the guy to check LTC2508-32 page17 figure9 buffer example.
Then I had a look on configuration suggested bellow, and I see ADC VCC filtered with LC filter and reference with 10uF as well wich serves as well as floating voltage divider for Vin from that circuit.
https://www.eevblog.com/forum/metrology/7-5digit-diy-voltmeter/msg1393950/#msg1393950
Then also reference demo circuit for LT2400 has 10uF in Vref and Vin.

So I decided to do these changes one by one and try.
Initial OPamp wass not definitively AD8628. I measured unity GBW and was only 570Khz while should be 2Mhz.
Anyway replaced with LTC2050HV which I confirmed to have unitary GBW of 2MHZ so should be real thing.
With this opamp noise was still on the realm of 600VPP (single sample) so I think even got worst.
Then still with LTC2050 adedd LC filter at VCC and got slight improvement.
Then added 10uF at Vref (was 1uF) and slight improvement again.
Then added filter after LT2050HV to RC 1K 10uF and big improvement from around 450VPP to the realm of 89VPP over 30 samples.
Then changed FO from ground to VCC after LC filter and additional 5-10VPP improvement in noise.

Then averaged with 15 samples - average (2PLC) and I get noise on the realm of 20-30VPP over 30 seconds.

So I think with large BW filter the noise is somehow integrating inside ADC. So now I need to understand what is best strategy to put the filters as reference designs have large caps right at Vin but I gess the filter should be some second order done by the buffer opamp and antialiasing filter just between Opamp output and ADC Vin, or?
This all is still with same ISO on SPI.

Before I do more stuf with mutiplex and respective buffers and build different board I need to understand how the filters need to be set and what the ADC is doing whit the signal feed to it. At least I undestood that the chopper can be used with the 1Meg input with some acceptable level of noise as long as Vin is filtered down to near DC or something.

[Kleinstein]

For testing the noise one could start with a shorted input. This eliminated the voltage reference as source for LF noise.

The RC filter directly at the ADC input usually should be as low in impedance as practical. So more like a 100 ohm resistor - that is about what lower power OP-amps are compftable to drive as an RC combination.
The main point is to avoid aliasing from noise at frequencies above 153 kHz/2 from the LTC2400 internal sampling.  Usually the input signal is not that fast an one could get lower in the cross over than absolutely needed. 10 µF is still quite large, but could be OK.

The RC filtering at the divider output side could be at least a comparable speed. So with the 1K*1 µF filter at the ADC with would be 1 M*1 nF. So a little more than the 22 pF shown.
Because of the noise from the divider more filtering can make sense, as long as it does not make the system too slow.

For the noise values the units are somehow not right ( maybe µVpp ?) and it is not clear if this is noise at the very input of noise scaled to after the divider / at the ADC input.
It would make sense to look at the noise after averaging over something like 20 ms or 40 ms to suppress mains hum.

[jorgemef]

Hello,

With the input shorted to GND the range of the noise output by the ADC is 50uVPP with average 20uV. This with single reading andwithout averaging.
Sometimes it jumps to 40v(Vref value). Could this jump be due to some out of sync bit or the internal cap not discharging somehow? It seems not doing that when not shorted.

When I measure the reference in circuit with Keithly2000 (PLC1) its range is 6-9uVpp, so around 1,5ppm noise read by Keithley.

So my reference is too noisy or not so much?

BR,
Jorge

[Kleinstein]

Some points going all the way to 40 V sounds like a digital problem, like getting out of sync.

For the noise test the RMS value can be a bit more convenient to measure than the peak to peak value. The RMS values tends to have less scattering than the peak readings. So one can get an estimate on the noise faster.

With readings faster than 1 PLC one gets a mix of noise and hum and this could be a bit difficult to handle. Precision readings usually want to suppress the hum. It would make sense to define a usefull averaging (some 1 or 2 PLC worth of data) that suppresses hum well and use this for most of the noise tests. A noise level of 1.5 ppm_pp is not that bad. Part of the noise could also be from the Keithley meter.