Power supply topology - will it work? (Control theory, stability)

[Yansi]

Again at the bench!  Thank you guys for discussing the problematic in such detail. Although I do not understand everything now, I might in the future, when I will grow up and be like you guys 

I might have not specified in the beginning, that the whole "supply madness" is a part of my project designing a usable "high voltage" regulated supply 0-400V 0-300mA. There aren't many of those real usable designs on the web, so I accepted the challenge to make one. Sorry for not being clear from the beginning, but originally I have asked due to my colleagues concerns about the topology might be inherently unstable - which I am glad is not.

I do understand, that there are many ways to design such supply, but please respect this is my first (or not exactly first, but first which might work) trial to make such PSU, so some compromises have to be done

salbayeng: Thank you for the tip to use cascode! I might try that one in the next better prototype. Gate-Source zener diode will also be added, together with other at least two protection diodes in the circuit (the schematics posted here are nowhere near complete, more like describing the principles of the regulation loop)

Kleinstein: Yes, current limiting is what I need to do next. Or before I do, I need to think out how to merge the voltage and current control loops.

Could you please help me evaluate my ideas for merging the control loops?

One of the usual ideas behind current limiting seen in many other circuits is that the current regulator opamp drags the voltage regulator reference input down, through a diode. However I can't use that, as I would need the opamps output to go negative (one diode drop) to be able to drag the ref voltage down to zero.

The idea behind using the inverting amp as a voltage divider was that only unipolar supply voltage is required. Therefore I cannot use the "ref voltage clamp" technique, as I can't go negative, as described above.

What I thought was I could sum the opamp outputs through diodes and "hang" the gate with a resistor (or possibly current source) up  to the positive supply. The schematic is below, image A. This circuit has a dangerous flaw: To be able to control the mosfet fast enough, the source current through Rg might be high (some tens mA). That means the diode voltage drop will be quite high and also the opamp output saturation voltage adds up. This means the gate voltage cannot be brought directly to zero, but only about a volt or so. (one diode drop + opamp sat.)

I think better solution might be to use the B variant on the schematic below. The diode drop is compensated by the Vbe of the transistor. So when the cathode of D1 or D2 is at GND level, the emitter will be very near GND too. Also the current through the diode and opamps output will be low, resulting in low saturation voltage and the widest range of gate control voltage down to almost zero. The emitter resistor Re might be also replaced by a current sink: A simple two transistor one (adding few hundred mV of drop) or likely just JFET as a current sink?

What do you think about this idea? Is it a good enough solution or are there similarly simple but better ones? How will this influence the control loops?

Thank you!
Yan


//EDIT: Just a thought: A diode accross E-B of the emitter follower might speed up gate discharge, as the opamp sink current ant I(Re) current will sum.

[Kleinstein]

Both ways for combining voltage an current regulation can work. For most MOSFETs a gat voltage in the 0.7 V range will not turn on the MOSFET. This is especially true for older types suitable for linear operation. The version with extra emitter follower also work an has the advantage of slightly more driving power for the gate capacitance. So it can slightly speed up the output stage, which usually is good for the control loop (usually no changes needed, but might be possible for faster regulation). Likely the voltage range for the gate voltage is quite limited - so the resistor can be good enough.

If needed one could add an additional drop, so that the OPs need a higher voltage to turn on the output stage.

For the control loops one might consider moving the capacitor from the OP output to the source resistor - this somewhat limits wind up if current control is active and thus speeds up the switch over from CC to CV mode.

The extra cascode stage is not that important unless one wants a really fast regulator. One can als o use a similar configuration to combine two transformer taps, to reduce heat production: use the one FET or BJT as a cascode for the higher voltage tap and use a diode to provide power between the two power transistors.

[Yansi]

Thank you for confirming. I will modify  my circuit on veroboard and test.

Sure 1V should not open it, but still I don't quite like it, so I came with a better solution.

I think I will not be bothered with extreme switch over speeds from CC to CV in this case. I think the best solution would be to use similar circuit like in the LM12 datasheet, where transistors are used to switch in or out the oapmps local feedback RC cell. But it might be an interesting thing to test or compare, if there will be any improvement (remember we might have some or more capacity on the PSU output, so extreme switch over speeds aren't possible either)

I might use the cascode configuration in another project.  If I am not mistaken - Keithley 2600 series SMU use similar cascode arrangement, aren't they?

This time I have designed a stepdown preregulator, no transformer taps switching. The project goal was to use cheaply available transformers 400/230V (connected in reverse) we use here often in industrial control systems to obtain 230V control voltages from 3ph power systems where connecting a load between phase and earth is not possible (like 4 wire only 3ph supply after an RCB). These transformers can be bought like really cheap and are safe, usually double insulation rated.

[Kleinstein]

The circuit in the LM12 data sheet looks strange / interesting, somehow using the transistors in revers too. I am not that sure if this way can easily be used for this topology. Usually current regulation is relatively easy in this topology. Somewhat opposite to the emitter-follower form, where voltage control is a little easier, but current control can be hard.

The output capacitance is not that large yet so one might still want a reasonable fast transition to keep overshoot within bounds. If you look at regulators using the emitter-follower topology for comparison, the visible output capacitance might be smaller, but quite often there is some more hidden in the circuit. A slow responding current limit might have a similar effect as some 1000 µF of output capacitance.

There is also an easy option to add just 1 or 2 diodes as a kind of shunt regulator to provide something like a -.6 or -1.2 V negative supply for the OPs and regulator circuit, as long as there is only little current drawn from it. So keeping it single supply might not be the highest priority.

The Keithley SMUs use some kind of cascode type circuit to use more than one raw voltage / transformer tap, but also some parts to divide a high voltage over several devices to get better SOA. But things get more complicated as the SMUs have a 4 quadrant output stage. This type of regulator is more like 1 Quadrant, maybe extended to 2 Quadrants if one wants to.

[Yansi]

I have actually tried the transistor-switched comp. cells in one of my projects few months ago - it also was 4 quadrant +-3V +-5A supply I tried to design for local university, but before I finished a PCB, they changed their minds and didn't need anything. It worked quite well.

The design goal is really not to use *any* negative supply at all. I don't like this in PSUs - one have to careuly look for unwanted glitches in the circuits, where one rail ramps up or dies sooner or later than the other. Sometimes even extra protection circuits are required to get rid of such glitches. So this time I'd try without any negative rails if possible.

I will try the "B" variant of the merging circuit. The gate-ground voltage measures about 5.4V at 27mA load (just took random measurement what to expect there). Interestingly - I consider the 4.8V gate-source voltage rather on the high side while the mosfet being just barely opened. But who knows, maybe a higher threshold voltage.

I will use the B variant for now, without the CCS, just gate-ground resistor. I will try with 30mA drive current (will be sufficient?), meaning I need about  150ohm resistor down there.

[Kleinstein]

30 mA of current is already quite a lot, already more than an typical OP deliver. So at least with such a high threshold the resistor should be ok. One could even use an emitter-follower NPN+PNP push - pull stage, driving the PNP from the diodes.

[Yansi]

Yes I have also thought about that. I think the PP stage should be with at least some base-to-base voltage or ideally some bias current, otherwise I am afraid the "hysteresis" or "crossover distortion" or how to name that might be a trouble for the control loop. But this complicated current boost stage might be more complicated than what is really needed, so I'll try  the simple first.

If I weren't so tired today... yaay. Still just writing here and doing nothing, the soldering iron is cold. 

[Yansi]

With a little help of coffee, the circuit mod is finally done. Rb=2K2 (round about 2.5mA to the opamps), Re=150 (did want to try 180, but couldn't find any  )

Circuit still stable, step responses hasn't changed much, if at all.

Now I should cobble together the current regulator on the veroboard, so we can have some other thing to play with. 

[Yansi]

What an epic win! 

I have put there another opamp as the current regulator. Did not bother to connect any feedback cap across the opamp, turned it on to see if it at least works, while expecting it to oscillate wildly when the current limiter kick in. And guess what: Nothing! And then I noticed it does limit current and is stable without any additional R/C. (Only 22k resistor in the inverting input)

So the high voltage PSU prototype finally works! Tomorrow I will test step responses of the current regulator and the CC/CV switch over. Thanks so far very much for help, now some bed time is needed! 

Here is the photo of the little bastard.

[salbayeng]

Step response testing:
I just connect a small relay coil to a signal generator set at ~ 1Hz (10v output into 600ohm drives a 12v 1000ohm coil nicely)
use this to switch your dummy load, really only good for 100vDc per contact, 2 in series will get you 200VDc,  more than that and you will need MOSFET.
Note that 0-10% transient responses are different  to 10% TO 100% transients.

Note re current limiting: if you have integrators in your voltage loop, then applying current limiting after the integrator will cause the capacitors to charge up fully, at that point the inputs of the opamp will float away from each other, and it will take a loooong time to recover.

[Yansi]

I have made this for step testing this supply.  NE555 + suitable mosfet and bunch of resistors (value selected through the switches), trigger out to the scope.

[salbayeng]

Nicely made dummy load!
I used to make them neat when I was younger, but after you've killed 4 or 5 of them, you get a bit sloppy!.
See attached for a dummy load and 20v 40A supply for testing a 24VDC distribution system
and a nice looking one (on the outside!) I made maybe 20years back (the DPM and fan is dead and some switches too)
I use these cheap 100W rheostats a lot too, only broken one so far!

[Jay_Diddy_B]

Blueskull and the group,

The difference is more than taking the Thevenin equivalent circuit and paralleling R1 and Rload. This is only a very small change. Typically R1 would be 100 times smaller the Rload, just for efficiency reasons.

This is the point that I am trying to make. This circuit:



Which represent the MOSFET stage and R1 as a transconductance amplifier, does not have the same transfer function as this circuit:



In the second circuit, the maximum size of the output signal, is the always less than the input signal. At low frequencies this circuit has very small phase shift.

In the first circuit, which represents Yansi's circuit, the amplitude of the output can be greater the input voltage. At low frequencies, and high value of load resistor, the gain is high and the phase shift is -90 degrees. The circuit is an integrator.

Regards,

Jay_Diddy_B

[salbayeng]

Yea, you're right, of course.  (an improvement on "right off course" )
I first looked at the output stage and thought to myself , "the output impedance is just R1 (as the MOSFET that shunts it in current mode is effectively infinite impedance)"
It's obvious if you consider the output swings 100's of volts but only a few volts across R1.
The maximum gain (at DC obviously) is simply 100k/R1.

The simple circuit you have is sufficient to explain what is going on.
I would add the embellishment of
(a) the gate resistor and miller capacitance but guessing 300R and 1nF  puts a pole in at 500kHz, of no concern
(b) and also add the zero due to ESR 100uF + 1R is only 1.6kHz (I should probably find some real capacitor data and not guess!)

[salbayeng]

Tried to check on ESR for typical capacitors.
Most datasheets stop listing ESR above 100v rating, If I do some extrapolating based on tan\$\delta\$ and rated current, the quality 105C electros have ESR's from 3 to 10 for 10uF/450v. (say 3kHz for 5ohm + 20uF)

A datasheet for 85C rated capacitors is here: http://www.mouser.com/ds/2/88/SK-32353.pdf  this shows 26   for 10uF/450V , this gives a zero at ~ 600Hz

If Yansi were to use a 1uF 450v polypropylene  http://au.mouser.com/search/ProductDetail.aspx?R=0virtualkey0virtualkeyECW-FE2J105J , reasonable size (28x17x10) and 66c
This has tan\$\delta\$ < 0.1%  , which is <120milli as an ESR at 1kHz,  This would push the zero out to ~ 200kHz.

[Yansi]

Hi!

I am using X2 rated caps in the circuit, as I have many of those available and they are sufficient with voltage rating.
Currently the output cap is an 1uF MKT from Vishay, so not polypropylene but polyester: http://www.vishay.com/docs/28161/f1772x2.pdf
It has a an added series resistor of 1ohm, as you did recommend in the beginning.

[Jay_Diddy_B]

Yea, you're right, of course.  (an improvement on "right off course" )
I first looked at the output stage and thought to myself , "the output impedance is just R1 (as the MOSFET that shunts it in current mode is effectively infinite impedance)"
It's obvious if you consider the output swings 100's of volts but only a few volts across R1.
The maximum gain (at DC obviously) is simply 100k/R1.

The simple circuit you have is sufficient to explain what is going on.
I would add the embellishment of
(a) the gate resistor and miller capacitance but guessing 300R and 1nF  puts a pole in at 500kHz, of no concern
(b) and also add the zero due to ESR 100uF + 1R is only 1.6kHz (I should probably find some real capacitor data and not guess!)

Just to clarify this further.

You may not have seen this circuit before:



But if you rearrange the parts:



It begins to look familiar.



You have probably seen this before:



It is a textbook common emitter amplifier.

If you ignore Cout, the simplified voltage gain of this stage is Rcollector / Remitter.


The challenge with designing a (bench) power supply, is that you don't know what value of Cout or Rload somebody will attach. The load may not be a resistor. If the load is a constant current load the gain can be very high.

If you designing a power supply where the load and capacitance is know, it is a little easier.

Regards,

Jay_Diddy_B

[Yansi]

Hi! A little update: As the current limiter is working just fine, I left it alone and have begun working on the preregulator control loop.

Before I started with the preregulator, I have noticed an unseen problem in the circuit (you can skip if you want, really nothing serious or much interesting, easy solution):
Way back when we discussed how to merge the two regulator outputs, we had the choice between resistor or CC load for the emitter follower. The resistor works fine, sure, but there is a problem! If the regulator output goes into positive saturation (like "not enough input voltage"), the resistor in the emitter of the follower will get blown after a while:  It was calculated for 30mA at round about 6V gate voltage, which is fine. However when the saturation occurs full voltage (like almost 11V) appears on it and high current is gonna destroy it. So the CC load might be a better solution, than an over engineered (1 or even 2W) resistor, that won't see more than 0.2W very often. The overload is somewhere about 0.8W so 1W resistor is not such a big deal. But just wanted to point that out.

Preregulator: Is a textbook standard inverted buck (switch and choke in the negative rail, positive common) controlled by an UC3843. I have successfully tuned the opamp that controls the preregulator. Partial schematic attached. Vds is a voltage sensed from a mosfet drain, ground is still the positive output terminal. Works quite good.
Step response of the preregulator output is also attached. Supply set to 75V, then shorted for a moment. Preregulator holds constant 50V over the mosfet. The undershoot is about 6V, no big deal - caused very probably by a windup of the integrator - as the ramp down speed is limited by the discharge rate of the prereg output cap (depends on supply output current).
The LED on the schematic is an optocoupler to the COMP pin of UC3843. There is a mistake in the drawing, the LED should be connected of course against +12V, not ground (otherwise the polarity of the feedback is wrong).

Slight problem 1: At some level of PWM, the current mode control of the buck convertor is still very slightly unstable (at the currentmode side of thing - subharmonic oscillation, even though I tried to apply a slope compensation. (Maybe doing it wrong or completely another problem).  I will draw the complete schematic so we can look more in detail, where the problem might be.

Another slight problem 2: After adding the drain voltage sense divider, you know, across the mosfet... guess what, current flows to the PSU output even when the mosfet is fully closed. Meaning, when the PSU is unloaded, quite some volts are present - 180V or so to be exact. (voltage divider is formed from the two voltage sense dividers 800k / (800k+330k+22k) * LinregInputVoltage).
Now what to do with it? Low value resistor accross PSU output terminals is not a solution, due to very wide voltage range (the parasitic current flowing from up top is constant (as the Vds voltage is also constant), about 0.15mA. A small CC load on the PSU output would do. What do you think?

Thanks,
Yan

[salbayeng]

re problem 2:
If your switching regulator is connected to the real negative ground,  then use two matched voltage dividers, one for the prereg voltage, other for the drain voltage, and use the difference of these. With a bit of cunning you can bleed your setpoint voltage into one of these legs. So it's just one opamp needed.
The problem of the output floating up is to be expected, (and you will get leakage current in mosfet and on PCB's particularly with heat, moisture, aging, lint buildup) I looked at this and didn't have an elegant solution (else I would have posted it) , you need a Ptype device, but there is no footroom to drive it. possibly lifting the bottom leg of R1 by a few volts would allow a PMOS to be activated

Also note for the dropper resistor in the divider, use 3 or 4 in series , allow for no more than 200v per resistor, and ensure you use metal oxide resistors, rated at 300v.

re the first problem:
Cheapest is sometimes the best; use a 2w resistor is a viable option, there are some axial types in 1W package sizes, they get stinking hot, they have really thin steel wires so the body can be 250C, but not conduct enough heat to melt the solder.
You could use back to back diodes across the integrator cap, but difficult to decide which voltage to use, and you would need the low If, low leakage variety. Note this saturation problem is vaguely related to your problem 2 , like many elegant designs, things get real ugly when you have to contend with all the exception handling.

[Kleinstein]

To compensate the leakage current or current through the drain-source sensing circuit, one could add a constant current load to the output. One can use the (supposedly 12 V) supply for the OPs for this to provide headroom to make it work down to zero:

Have a PNP transistor with base connected to GND, a resistor (e.g. 10 K) from the +12 V (preferably regulated) to the emitter and the collector to the negative output. This would provide something like a 1.1 mA constant load, working down to about - 600 mV. So to avoid the possibility to get a slightly negative output one could lift the base to that about 600 mV (e.g. one diode drop - saturation voltage of the PNP). As the current from sensing the DS voltage is pretty constant one can compensate this also.
Unless for very high voltages the pre-regualtor should be set for much lower DS voltage. Usually something like 3-10 V should be enough. It is just to have some reserve in case the preregualtor can not follow fast enough. There should also be an filter between the two stage, to keep RF noise out.

For the gate drive, it might be a good idea to have a fixed maximum voltage limit for the gate - this would also act as an independent fast acting instant current limit, though not accurate.

[salbayeng]

I've combined , (and hopefully improved upon) Kleinstein's ideas.

(a) Inherent current limit of the main MOSFET (Q1) in my schematic , by voltage limiting the gate (to 12v in my schematic) , and setting the emitter resistors R4+R5 to produce the appropriate current limit.  I've added C1 so there is a fast current limit of ~ 20mA to charge up the output cap , and a slow limit of 5mA, obviously you can adjust these values as required.

(b) constant current pull down this is Q3 in my schematic (could be a PNP , I didn't have any HV PNP in my model library, and too lazy to import a model) , for a fixed current , connect gate to gnd, and omit D1, set R2 to 10k, and that's the 1.1mA source Kleinstein refers  to.
I've embellished it so it only comes on when the capacitor needs discharging. The big problem with my approach is the crossover, and discharge current is achieved by subtracting 2 x Vth and a zener drop from 12v,  so if any of these move around much it won't be accurate.
You could also split R2, and add a speed up cap just like C1 if you were that way inclined.

I've also set resistor values so the error voltage can swing through the entire 12v available , and now the upper 4-12v region controls the charging current, and the range below 4v controls discharge , given the mosfets have ~ 4v this went together better than I expected, so we have basically a class AB amplifier stage.

The simulation produced excellent response with no feedback around X1, although Verror was oscillating ~ 1MHz!
I took a wild stab at some compensation values, and it's pretty good now as shown with 100k & 1n , the opamp gain is 100 above 1.6kHz . and an integrator below that
The step response overshoot is about 1v at 300v ,slightly underdamped ,ringing at ~1kHz  ( I repeated sim with smaller timestep and relative accuracy and its still similar looking, so the sim might be believable!)
The closed loop responses attached (blue = 3meg, red=30k load) shouldn't be trusted, I'm not sure where the bias point is . The blue one corresponds to the observed step response.
The sim just applies a step change in the setpoint to and from 70v to 320v, I've stepped the load from 30k to 3meg, with 30k you can see the current limiting taking place, and you can only sustain ~ 140v across the 30k while in current limit mode.
There are figures attached for the output voltage, current, error voltage, and drain voltages.

[salbayeng]

Ok ,  I've managed loop gain plot (Using Jay_Diddy method), see pdf.
I've done this with 3 load resistors, 30k, 300k,3meg   red green blue for loop gain , and light shades of same for phase.
The 30k & 300k are pretty much under each other , the 3meg is different , presumably the mosfets are biased into a cross-over dead spot?

The phase at 0.01Hz starts at 180deg , and the gains level off (as the op-amp maxes out its gain)
According to the plot, loop gain is 0dB ~ 2.5kHz, with phase ~ 55deg.

[Kleinstein]

Adding a P-MOSFET in the way salbayeng did, is adding limited 2 quadrant operation. This can be an big advantage when is comes to recovery from large disturbance. This version needs an stable 12 V (preferably a little lower) supply and might be a little sensitive to thermal drift. The zener diode would need an individual adjustment, depending on the FETs to keep the dead zone small or even ensure class AB operation.

Adding the phase boost with splitting the source resistor is less practical. One thing is that it need a quite sizable capacitor, if R5 is in a much smaller more realistic range (e.g. 1-10 Ohms). The advantage of having the phase boost in the feedback divider is that it also reduced the bandwidth requirement for the OP and together with protection diodes it helps with the CC to CV transition without much overshoot (tends to be a little slow instead).

[salbayeng]

Yep I acknowledge it's not perfect, I just scribbled it on bit of paper to see if I could avoid having a current source on all the time, by simply moving Q3 gate drive across,
 I tried it on a sim and it worked better than I expected so I printed some epictures off and pushed it here for comment.

The "emitter bypass" cap wasn't primarily for phase boost, I would expect to use a shunt cap on the feedback for phase boost to improve HF regulation.
I had it working open loop just driving a trapezoid pulse into the gates, and it worked well, so just closed the loop as simply as possibly, R11 and C3 are the default values Simetrix drops in, and 100k gives a gain of 100 which seemed appropriate, I wasn't trying to get an optimal controller,  just wanted to see how well the crossover worked with a closed loop, heck even the 4.7v zener is the default zener, and I fluked about 100mV crossover overlap. Q3 is only a 50v MOSFET, but a quick edit of the spice file fixed that!.
The 1k / 500uF is intended to provide a time constant of 500ms, to approximate the thermal time constant of Q1, so it can draw more current for short periods of time.
While pea-size 560uf/6.3v caps are available as polymer dielectrics,  this brute force approach is unweildy with say 100R as the source resistor.
And you could do the "anti-surge" feature using smaller capacitors, a handful of resistors and a zener in the gate drive but it's less elegant.

I've used the PMOS threshold before (as a 3.8v reference voltage) to set pullup current in some active terminators in another project, and over ~ 60 units there was a 5% spread in actual currents, better than I expected , and those current sources also used an elegant method to reduce power consumption when not actively switching.

[Kleinstein]

The source resistor should be much smaller - even the 22 Ohms that the OP used are relatively large. Otherwise too much voltage (and power) is lost there. For the P-MOS the source resistor might be relatively large and the capacitor to boost the current for short times might be viable.

For a short time current limit a zener right at the output of the OP (or where the CC and CV signals are combined with diodes) is more effective. There just is no need for a very high gate voltage. This would also save the small resistor at the emitter follower.