Power supply topology - will it work? (Control theory, stability)

[Yansi]

Hello!

Just an interesting topology useful for high voltage power supplies, requiring only asymmetrical aux supply and opamp capable of working with (near) zero voltages (like 324 or 358 or any RRIO one). The question however is - will this one work?

A little description: Referencing the aux supply to the positive output terminal has a big advantage of driving the mosfet gate, no high voltage amplifying  stages are needed.
As the feedback voltage is negative related to the aux supply reference point an inverting amplifier is used to both scale the voltage down and change polarity to positive.
Then a regulator is used to control the mosfet, based on the positive feedback voltage, comparing with positive reference voltage, related to aux supply gnd.
R1 is used as a current shunt.

The regulator is the most difficult part: How should I determine, what type of regulator (R and C configuration) and compensating circuits shall I use so I can make the thing stable, even with added capacitive loads on the output?
Note: The integrating regulator might not be what the circuit really requires!

Schematic is attached.

Thank you for helping me 
Yan

[Kleinstein]

In principle this type of regulator works. Many of the HP lab supplies use this type. The nice thing is that you can use essentially the same regulator part for different voltage levels - from low voltage like 3 V up to 100s of volts with suitable power transistor.

The regulator might need a resistor in series with the integrating cap and an output cap with sufficient ESR or series resistor. One can even simplify the circuit by using the non inverting input for the feedback (and add a positive reference current).

Today one would use a simulation (e.g. LTspice) to check.

[Yansi]

Yes, I have also found later the non-inverting input can be used, by supplying a positive reference current. One opamp less, however this has the advantage of an high impedance reference input. (One would have to use an extra follower to supply the reference current, if high impedance control voltage input is needed).

What do you mean by "sufficient ESR"? User of the PSU can always connect a big low ESR cap directly on the output terminals.

How would you estimate the compensation values in a specific circuit design? (or to make a simulation? First estimate will still be needed)

Do you know any schematic I could reference to?

Thanks,
Yan

[T3sl4co1l]

Note that, since MOSFET source, and error amp, are referenced to +out, this is a negative voltage LDO (open drain output).  Which means, a better way to draw it would be... *waves hands around erratically*.  Well, you know.

You don't need ESR for stability of this type of regulator, but you do need a loop with enough means of control to realize that -- usually using the transistor as a controlled current source (which it is anyway, regardless of how you treat it -- the drain output in the linear range (FET current saturation) is CCS), with feedback to control that current precisely (rather than the quadratic to exponential dependancy on Vgs that a naked transistor has), and feedback around /that/ to set the actual output voltage.

ESR helps because of adding a zero in the loop response; ideally, ESR * C is selected so that the zero falls near fT (i.e., loop gain ~= 1), so as to improve phase margin.

Tim

[Kleinstein]

For this type of regulator the ESR of the output cap helps to get stability. Often something like an 0.1 - 1 Ohms ESR can work to provide enough damping in the 100 kHz range. Even with an external low ESR cap this damping will persist. With enough low ESR capacitance the ESR might not be needed anymore. However a capacitance without ESR can worst case loose its effect with an inductive load. The ESR has a similar function for stability as the relatively low output impedance of the classical emitter follower stage.

For the fist estimate of the tuning loop one can start very slow and than adjust in the simulations.
A good point to look at is the output impedance in the 10-100 kHz range. Something like 1-10 Ohms is realistic unless you have a very slow of fast output stage.

In the simulations looking at the output impedance (use AC source as a load and look at output voltage) is a good way to check for stability with different load conditions. If the output impedance has less than 90 degree phase shift everything is stable, no matter what (passive, up to +- 90 deg phase shift) load is used. One still needs to check transient response for unpleasant surprise of nonlinear effects from saturation or similar. Linear stability is required but not sufficient for good regulation.

[Yansi]

OK, thank you both for some hints. But may we try with some specific design situation, so I can better understand the processes involved?

Let's say I want to build a regulated DC supply, 0 to 400V using the topology in the first post (here attached again). The max output current will be 150mA. 
The ref voltage has been chosen to be 5V full scale, so the inverting opamp shall have a transfer of -1/80. So set R5=800k and R4=10k.
The current shunt has been selected R1=22ohm (3.3V drop per 150mA) and gate resistance of whatever some hundred ohms, say 270.
I want the output capacitance of the PSU to be as small as possible, yet it has to be stable with all kinds of additional loads. How should I estimate the required output cap Cout?
How will I estimate then the loop bandwidth and compensation values? (R3, Cfb or other ones if needed).
What shall be the first step in this situation?

Thanks,
Yan

[Jay_Diddy_B]

Yansi,

You can start the control loop modelling with the attached LTspice model.

Here is the model



This the results



I haven't made any attempt to optimize the loop.

Note: I have essentially designed this as a negative output unit. This is because the positive terminal is the small signal ground.

Regards,

Jay_Diddy_B

[Yansi]

Thank you for the sim!  I'd now better install LTSpice and learn the damned thing  (Sorry, my best sim yet is the soldering iron, heap of components and a bunch of meters)

How did you estimated the compensation values?  (C1, R3) and how can one figure out C3 R7 were also needed?

What are those arrows marking in the bodeplot?  Is that the "crossover frequency" and how did you use that to derive the component values?

Thank you,
Yan

[Kleinstein]

The part with C3, R7 is known from lab supply circuits. They usually need it to get stable with large capacitive loads, but it also changes the rest of the adjustment. So better include them from the beginning. The rule of thumb I know is having R7 about 1/10 of R5. The exact value is usually not that critical.

For R3 and C1 values could be just ballpark figures, e.g. from an other supply circuit or a little higher. If one really wants one could calculate it up front to get the desired cross over frequency ( 0 dB Gain for the loop gain, marked with arrow). But with a simulation if could be just a crude guess and one correction step.

The circuit likely will need protection diodes to GND where R4,R5 and C3 come together.

With a MOSFET power stage one might have to watch the performance at low currents, as the MOSFET is rather nonlinear and much slower at low currents. So some minimum load (or even 2 quadrant operation) might be a good idea if one cares about minimal output capacitance.

[Yansi]

I think guessing / trying component values won't work here at all. You have at least six components you might change: double RC compensation and the output C+ESR. The probability of guessing these correct (enough) by trial and error is almost zero.

I have already built the circuit (few days ago), but had serious troubles making it to behave nice. It does not oscillate, but that is the only thing it does right. The load change step responses were ugly as hell. My friend even had told me, that the circuit topology is incorrect and will be always unstable - hence why I have asked in the first post about it, because I was almost sure, this has to work.

I have tested only so far the step responses of  "no load at all" versus "some load".  Circa 250V input, about 30-50V output, up to 30mA load. (Cannot test higher voltages or currents, as I don't have  suitable equipment and mosfet in the circuit: STP6N80K5 being used currently)

The step response at the time of connecting some load is I think good enough, however disconnecting the load (to no load) produces ugly ringing.  The bigger the output capacitance, the longer it rings with a lower frequency. And it is not any kind of high frequency oscillation, it rings at kilohertz to Hz range for a 100ms or more sometimes.

But before posting further, I need to make a better measurements of the step responses and use a better measurement technique.
Maybe I want something that is simply not possible with what components/circuit I have.

[Kleinstein]

There are not that many degrees of freedom in adjusting the compensation. The R5/R7 ration is relatively fixed. So there are essentially only the 3 caps c1,c2,c3 and the series resistance. The caps also are responsible for different frequency ranges: the highest frequencies are mainly influenced by C2,R6 and only a little by C1. The intermediate frequency range is influenced mainly be C1 (or more accurately by C1*R3/R1/R4*R5) and a possible resistor in series to C1. C3 is usually important for the lower frequency range - though the 100 pF value shown is rather small, but R5 is also large.

So once you have a reasonable start, one can optimize the three caps relatively independent So it's not one system with 6 interacting degrees of freedom - which would really be hard, but more like 3 systems with 1 or 2 parameters with relatively little interaction. Optimization is still not easy and will take some time and simulation runs.  One may not find the absolute best - but defining what is best is already difficult. It will be a compromise on performance at different loads and tolerance to parasitic effects and not so perfect models. It does not make sense to optimize to far in the simulation, as really life will be a little different - so it also has to work with slightly values.

The more annoying part is that the "best" parameters also depend on the DC current. So one has to find a solution that works at high and low currents. Here it can really help to have the output stage in a way that it depends less on the current: this could be an extra local loop or maybe using feedback from the source resistor instead of the gate driving part. If performance of low currents is important, I would consider using a output stage that can work 2 quadrants.

The next possibly tricky part could be nonlinear effects do to a kind of windup of the regulation loop - so sometimes even if everything is fine for small signal tests, the a regulator circuit can still oscillate after large steps with certain loads. However this also applies to other topology.

It can be still a little tricky when doing it with hardware, unless you have good instrumentation (response analyzer). However in the simulation no limitations from instrumentation: for example one can still get the loop gain for an unstable system. So one can directly read loop gain or output impedance or step response.

Having a regulator of emitter follower / source follower type can be a little easier to tune - at least if you don't need a lab supply that includes current regulation too.

[Jay_Diddy_B]

Hi,

Let me see if I can explain how to do analyze this.

Modified Model

I have rearranged the model, without changing the circuit or the component values. I have added labels OP_U1 and OP_U2. I have divided the circuit into three blocks, the power stage, error amplifier and the divider stage. The loop gain is the product of the gain of all three stages.



Results




The results show that the error amplifier has a single pole slope, 20 dB/decade and 90 degrees of phase shift. The result deviates from this at high frequency because of limitations in the op-amp.


The divider stage has a pole zero pair. This is often used in power supplies to generate phase advance or phase boost. Again the result is textbook, until the op-amp characteristics creep in at the higher frequencies.

The output stage is the most interesting. The other blocks, nothing changes with load current, output capacitance etc. but in the power stage everything matters. The Power stage is a single pole from the output capacitance and the transconductance of the MOSFET. There is also a zero formed by Cout and the ESR of the output capacitor.

Changing Cout

I have introduced the .step directive to change the value of the output capacitor through a list of values.



Results from Changing Cout.




I hope this give a little insight in to how to model this circuit.

Regards,

Jay_Diddy_B

[Yansi]

Thank you for detailed explanation how to simulate the loop stability.  Will install the spice soon and try to bite it. Currently the soledering iron is still the easiest for me. 

I have finished building the load step test jig, so I can finally measure the response.

The setup was as follows: Schematic with values attached.  Input is around 260V, output set to 70V.  Load switched on-off is 1k65 resistor (so 42mA  or nothing).

Step responses shown below. Tested first with 1uF 1ohm  only, then added 10uF ellytic cap directly on the output (no "additional ESR").

Could you please evaluate the results, somehow? I am not sure how that should look like when correct, but I am concerned the ringing when load is switched OFF is really not good. I have tried fiddling with  C3 and C1, increasing their values slightly (up to 0,5nF or so), but not much effect on the step responses. Increasing C3 too much (0,6n) makes it oscillate.
Note the very long ringing time (and period) at load off, especially with the additional 10uF cap.

I will also try stepping the load  between 20 and 40mA, what will be the difference.

Thanks,
Yan

EDIT: Schematic added. Note V2=875mV.

[Jay_Diddy_B]

Yansi and the group,

I ran the transient test with this model, 10uF capacitor:



Here are the results:



Fairly similar to what you have on the hardware.


Modified Model

I have modified the model to improve the response:



Here are results from the modified model:



Try modifying the hardware and see if you get a similar result.

You may need to add load resistor, around 1mA to set a minimum output current.

Regards,

Jay_Diddy_B

[Kleinstein]

Doing the step response all the way to zero current is difficult for the regulator. Some of the ringing when switching the load off can be from nonlinear effects (having the MOSFET turned off for some time). This might need additional measures. Also the MOSFET gets quite slow with only the 800 K from the divider as a load.

The LM324 is a quite slow OP and thus one can not expect a very fast response. To avoid the dead band from the output stages one could try an additional 1-2 K to GND at the OPs, especially OP1. A faster OP (like TLC272) could help. The response is relatively slow, but much of this can be attributed to the slow OPs. One could ease a little on the OPs by reducing R1 to maybe 5 Ohms.

Some ringing like with the 10 µF capacitive load is normal and cannot be avoided. However the slow ringing indicates a still slow regulator and normally such heavy ringing should only happen with much larger caps (like 1000 µF).

[T3sl4co1l]

Note that ringing is a symptom of control loop stability, phase margin and all that.

The total (peak) magnitude of over/undershoot is determined by the capacitor, at the very least.

Simply, the control cannot respond instantly, so until it does, the output has the relationship:
I = C * dV/dt

For a delay of, say, 1us, and a specified stability of 1% or better (i.e., +/-1V transient out of a 100V supply), and say 100mA load step, the capacitor must be V = I * dt / dV = (0.1A) * (1us) / (1V) = 0.1uF.  Or more for longer time scales, or tighter regulation, and so on.

For the ESR to matter, it has to have a comparable voltage drop, i.e., on the order of (1V) / (0.1A) = 10 ohms.

There can exist no such arbitrary rule as "1 to 10 ohms ESR".  A very low current, very high voltage regulator will see even 100 ohms as a short circuit.  Whereas a very low voltage, high current regulator will need as many milliohms to have acceptable output impedance.  Only the time constant ESR * C matters, and it will be proportional to the loop time constant.

This way, you can figure out the ballpark C and ESR that is desirable for any power supply.

Tim

[T3sl4co1l]

Note that the overshoot is excessive in the above simulation, because the op-amp has to slew a huge voltage range (from cutoff to normal operating voltage), and is limited by its own speed, and the compensation network across it (where the capacitor is dominant -- note that the resistors are both 10k, so an input step into that amplifier will only make an equal amplitude output step, with slew rate limiting added, and rising slowly over time as the capacitor charges).

If a quiescent load is introduced (say, changing the ISTEP from 0 to 42mA, to 10 to 52mA), then it will behave much nicer.

It will behave nicer still, in the current range where the 22 ohm source resistor is dominant (i.e., gm > 1/(22 ohm)).  This is where the MOSFET becomes a nearly linear transconductance amplifier (voltage in, current out).  In this region, the control loop response no longer varies with average current level.

Tim

[Yansi]

Thank you for responses guys!

I have made another set of step measurements. This time at 40V output (I had to lower the output, otherwise the mosfet would get  some hot soup!) as my set of resistors for high voltage loads is not variable enough. When stepping from 27mA to 51mA, the responses are much nicer. With the 10uF added load, the ringing is quite damped now.  Without the 10uF load, the step from 27 to 51mA yields only about 1.2V overshoot and undershoot. With the 10uF cap connected, both under half a volt. I should also test with larger capacitive load like 100+ uF, but am afraid the mosfet might get killed, as no current limiting is being implemented now. (But sure will be soon)

Please note the 10uF cap should be external load to this PSU, the internal cap should be only the 1uF foil plus the 1ohm ESR.  By the way, isn't this similar function to the "zobel network" used in many audio amps (to present a load at higher freq)?

Yes, the LM324 is slow. But was the first opamp in reach with "input commonmode include gnd" and also being a quad OPAmp. The other two will be later used one for current limiting and one for pre-regulator control. (a stepdown converter will be used - prototype is mostly finished and seems working and happy).

TLC272 you say? I have a feeling I should have few TS274 opamps somewhere. Should be even faster and the quad I need. But let me tell ya, I made a mistake soldering the 324 directly to the veroboard. Doh! Thanks for the tip, I'll try to find them.

The 22ohm current shunt has been chosen due to two things: I wanted larger sense voltage, so that the opamp's offset voltage will have less influence on stability. 22ohms will result about 3V at 150mA. (however the target is 300mA using two IPW90R1K0C3 in parallel - but that might be in a future). The second reason I have chosen higher source resistance was me thinking I will linearize the mosfet output characteristic - but I might be wrong ??

I will try to desolder the 324 and put there a TS274 socket and TS274 in it and try again.

T3sl4co1l: Interesting to know, I had thought there would be a more complicated relationship. Will try to take that into account. What would you suggest to be the spec for a decent amateur built 400V 300mA general purpose PSU?

[Yansi]

TS274 has been successfully found and socketed on board. It works. Without touching the compensation networks, the overshoot/undershoot are slightly better, say by a tenth of a volt. (1V instead of 1,1V). It also seems there might be less damping when the 10uF load is used.

After having modified the compensation according to your latest sim, the results are way better.  480mV no cap, 280mV with 10uF load.   

[Jay_Diddy_B]

Hi,

I am not a big fan of this topology from a control theory point of view.

You start with a pole in the error amplifier, this is because there is a capacitor in the feedback loop to ensure that there is no d.c. error.
The power stage is a transconductance stage with a load capacitor. This is another pole.

So we have a double at the origin (or low frequencies) The combined double pole has 180 degrees of phase shift.

The power stage pole moves with the addition of output capacitance as we have seen.

To stabilize the loop I added a pole zero pair in the divider get phase advance at the frequency were the gain = 0dB. I also added a zero, by placing a resistor in the feedback path of the error amplifier to remove the error amplifier pole.

There are other contribution to consider.

The zero formed by the ESR in the output capacitor is included, in the model, to show its effect. With the values shown it is too high frequency to be useful, it is higher frequency than the loop bandwidth.

With the values that I have chosen there is little benefit to using faster op-amps. The gain of the op-amp sections is determined by the passive components around the op-amps, as it should be in a good design.

Regards,

Jay_Diddy_B

[Kleinstein]

It is a good idea to do the testing with a lower voltage, alone for safety reasons. With a sufficiently fast OP, the higher source resistor is not such a big problem unless it gets too hot.
The LM324 might be still acceptable for it's bandwidth, but the slew rate can be rather poor and the output stage shows quite some cross over distortion when going from current sinking to current sourcing.

I would at least add minimal current limiting with a transistor driven by the voltage at the source resistor and turning down the gate.

There is not that much difference in the control loop when you go to the alternative emitter follower topology. In a unified picture one can also consider other output stages as controlled current sources, just with an addition impedance to ground, to take into account the usually lower output impedance of an emitter follower. However at low currents even the emitter follower will not be that low in impedance to be useful. So one generally still needs the output capacitor of similar size. Some of the capacitance might be moved to the base side of the transistor and thus will not be directly at the output - but the effect is essentially the same in the good and bad.
It's only on transients of increasing load, that the than low output impedance can really help to limit drops in output voltage, so that an slower control loop can be acceptable.

On the downside one also has to make sure the output impedance of the power stage is well behaved and does not tend to oscillate by itself.
Things get better with a push pull output stage, that has a low output impedance even at low currents.

@blueskull:
I think it should be *k4 not +k4 in the transfer function. So no such easy way to prove stability.

The tricky part is to make it stable even with variable load.

[Jay_Diddy_B]

@blueskull:
I think it should be *k4 not +k4 in the transfer function. So no such easy way to prove stability.

Since A(s)=\$ \frac{G(s)}{1+G(s)*H(s)} \$, multiplying \$ \frac{1}{G(s)} \$ on both nominator and denominator, we get A(s)=\$ \frac{1}{\frac{1}{G(s)}+\frac{1}{G(s)}*G(s)*H(s)} = \frac{1}{(k1*s)*(1+k2*s)*(1+k3*s)+k4} \$

I don't understand, intuitively, why the gain (or attenuation) of the divider is treated any differently than any other gain block in the control loop.

If I increase the gain of the feedback and reduce the gain of the plant by the same amount, the loop gain is unchanged.

The loop gain is the product of all the gains in the loop.

Regards,

Jay_Diddy_B

[Kleinstein]

Calculating the forward gain and treating the regulator as an amplifier from reference to output may not be enough to check for stability. We actually do not care very much about that gain, as the reference is not really changing fast. The important part is the loop gain, this G*H and the output impedance, thus the response to an current acting on the output.

[salbayeng]

The output transistor M1 can be augmented by making it run in cascode mode, this way you opamp isn't sinking all that miller capacitance.
Simply break the connection between M1_Source and R1, put a NPN here , a simple NPN bipolar will work 30v 1A or a small NMOS.
So the opamp now drives the base (gate) of the lower transistor, and the gate of M1 goes to +12 via say 20R (to stop VHF oscillation).
The cascode configuration can also be used with depletion mode FETs (Like the 1600v SiC devices).

You will need zeners/diodes to 12v and/or "gnd" to stop the source node flogging around if the output arcs.
(You need something from gate to source anyway with your existing circuit, otherwise arcs will cause punctures through the oxide).

Note this idea is tossed in as a discussion point only, if your circuit works fine then don't mess it up.

Note you can use a depletion mode MOSFET to make a simple bias supply, as per figure below, this is a 11v output LDO, with input voltage range 11.1v to 250v , Iq is ~ 100uA.
(Output current is limited by heat dissipation, so maybe 2mA at 100v).
This is thrown in for interest only, as it won't work in your circuit as it will drag the unloaded output up.
(Your circuit could probably do with adding a PMOS to drag the output down anyway)

[Jay_Diddy_B]

It seems like the circuit is stable. If my derivation is correct, the transfer function should look like this:
G(s)=\$ \frac{1}{k1*s} * \frac{1}{1+k2*s} * \frac{1}{1+k3*s} \$, where k1 is constant for integrator, R3*Cfb, k2 is constant for FET corner frequency, R2*Cequ, and k3 is constant for output filter, R1*Cout
H(s)=k4, where k4 is feedback factor, k4=\$ \frac{R4}{R5} \$
So, the overall transfer function can be simplified as: A(s)=\$ \frac{1}{(k1*s)*(1+k2*s)*(1+k3*s)+k4} \$
It looks stable to me due to the existence of k4 in denominator. Overshooting is possible, but this topology will not oscillate, at least.

Hi group,

I don't agree with the analysis that k3 = R1 x Cout.

Models

I have generated 3 models on the same schematic to make it easier to compare the results.



Vout_1 is a simple model a single pole with a frequency of 1/(2pi x (R1 || Rout) x Cout) but, if Rout >> R1, then Fo = 1/(2pi x R1 x Cout).

Vout is considering the MOSFET and R1 to form a transconductance amplifier. This would be a pure integrator, except for a zero at 1/(2pi x Cout x Rload)

Vout_3 is essentially an op-amp circuit with the same characteristics of Vout, but with a 180 degrees of additional phase shift introduced by the inverting amplifier. The voltage controlled voltage source E1 can be considered to a power op-amp with an open loop gain of 100K. This circuit is recognizable as an integrator with a zero formed by Cout and Rout.

Results



The results suggest that circuit formed by the MOSFET, R1 and Cout is not the same as an R1 x Cout network, because it has a gain greater than 1 at low frequencies.

Regards,

Jay_Diddy_B