Power Factor Correction, Discrete Control Circuit (For BCM)

[T3sl4co1l]

Not something you see every day:
https://www.seventransistorlabs.com/Images/Discrete%20BCM%20PFC.pdf

- PoC.  Not "commercially ready".  Do try it yourself, critique, and improve.  (Rules/goals? Generally I like to prefer transistors as much as possible for discrete designs; stuff like TL431 / op-amp / comparator, logic gates, etc. being acceptable when the complexity is just too bothersome to build out otherwise.)
- Input voltage and output current range are fairly narrow, haven't put much thought into it yet as far as why, or how to improve it
- Output voltage regulation not implemented (control input (R15) is trivially replaced with an error amp, once range issues are addressed)
- It really works!  At least in the range that it does, input current tracks input voltage, giving high PF.
- ...I don't have a measure of PF, but check the waveforms, they're not too bad, considering.

Principle:
When a boost converter is held in BCM (Boundary Conduction Mode: inductor current just returning to zero as the next cycle begins), and when it is charged with a constant on-time, then input current is proportional to input voltage, and high PF results.  We then merely vary the on-time to vary the output power.

Circuit explanation:
Q10-Q11 form the gate control latch/flip-flop.  Q12, Q4, Q5 form the gate driver (inverting, with CCS + emitter follower pull-up, and relatively strong pull-down from Q12 via D11).  Logic is implemented with a current-sourced RTL, or I2L, sort of scheme: R8 and R9 bias the collectors up, and either that current flows into the collector, or the various bases wired in parallel.  It's not actually I2L because the base resistors allow me to cheat and get actual fanout.  Voltage swing is small and speed is quite reasonable.)  The pull-up currents are reused by the timer and driver CCSs.

On the left, pulse timing.  While Q7 is on, FFNQ is low, so CT is allowed to charge slowly through Q3.  When the voltage rises a Vbe above Q8's base, it shunts the pull-up current, diverting it to Q10, flopping the flip-flop; thus a monostable timer is made.

On the top, quasi-resonant feedback.  When SW dips down below RECT, Q2 is forward-biased, emitting a pulse to TRG.  Q6 gates this pulse (dependent on FFQ) to start a new cycle.  Thus it's a monostable with retrigger, and that works to operate in BCM.

The cycle doesn't restart reliably: at low input voltage in particular, there isn't enough signal to trigger Q2.  In this case, and also for startup in general, an external source (function generator, V2) provides stimulus, and Q1, level shifting.  (Also as a result, there's zero-crossing distortion, i.e., little current is drawn at low input voltages; this probably only costs a few percentage points of PF.)

Since the power source is just a spongy little 12V 600mA transformer, little is needed for a power stage -- a relatively large inductance to get Fsw ~ 100kHz, and a mere IRF510 and 1A diode will do.  C5 is very overkill, just happened to be handy.  EMC improvements are indeed shown: the relatively long lead length of C5 was found to be excessive, and the combination of a drain FB (L2 is actually threaded onto Q7's pin), plus local bypass C4, got that under control.  Increasing gate resistance, or FB on G or S, was found to have relatively little effect, at relatively high expense to switching loss -- for example for R10 at 100-220Ω, is enough to get rid of the ringing, but switching is rather sloppy.




Input waveforms: RECT (Ch.2, top) and IS (Ch.3, bottom).  10x probes, so that's 13V, 150mA input.  Classic flat-topped power here, but current is following that just fine as it should.  As you can see, a lot of zero-crossing distortion, where Vin isn't enough for Q2 to trigger on, more or less.

This is at 30V output, so 2.7W.  13V * 0.15A = 1.95W... uh well, hmm, don't worry about that huh...
That's better... DMM says AC input is 14.5V and 207mA RMS (3W at PF = 1).  Not sure why the rectified values don't match..?




Zoomed on the leading edge.  There's some fluctuation in what phase the switching starts at, but this is a typical example.  You can clearly see the slow rising and sharp falling edge, due to the large boost ratio at this point; and that it goes to zero, or maybe slightly reverses (hard to say from here, but at least stray inductance shouldn't be a big source of error, at these currents and rates), as we expect for BCM.




Zoomed near the peak, also half horizontal scale to get a better look at the waveform.  The extra spikes are due to the switching edge coupling through; without EMC measures, this was a taller, wider tone burst (ringing).  Now they're short enough to even alias at this sample rate.  (In Peak Detect mode, the turn-off transient shows up to 4 div peak; turn-on is less than a div -- which more or less confirms adequate BCM operation is achieved.)




And zoomed even further, gate waveform (at G3).  Rise and fall are nice and sharp, preshoot I think comes from Cdg (again confirming BCM or something near it), and... not sure actually how it undershoots at turn-off, doesn't seem like that should be an inductive effect.

I have one component on the breadboard, not shown on the schematic: a 4.7k from G3 to GND; this is so I can break gate drive (e.g. remove R10) to disable the output.  The turn-off looks normal (returns to 0V more or less immediately) without it.  Huh.  B-E recovery (storage) in Q5 maybe..?!




And drain waveform (SW), here delayed to 1.6ms hence the more modest levels; the quasi-resonant recovery is basically just rail-to-rail, and a small blip accompanies turn-on.

Tim

[T3sl4co1l]

And in case you thought I was bluffing about breadboarding.



Tim

[TimNJ]

Very nice! 

So, you are adjusting the on-time manually by varying R15, right? If you increase the load, and then adjust R15 to increase the on-time, it can't handle the new load? In what way? For (most?) off the-shelf controllers, on-time is constant if line and load conditions don't change. So I guess on-time is a product of output error voltage. Positive load step -> output voltage droop -> increase on-time until error voltage is zero, or something along those lines. I wonder what an actual implementation looks like.

---

A more general question about BCM - what affects the quality of the wave shaping then? Let's pretend that we have an ideal PFC stage that can draw current even when the input voltage is very close to 0V.

In a CCM PFC stage, there is a current reference (derived in some way) and actual measured inductor current. The two are compared and the on-time is varied such that current error is brought to zero. But, this loop requires compensation so that the on-time is adequately modulated throughout a given cycle.

I see BCM as almost "naturally" (??) modulated, in that, if the on-time is (theoretically) always the same throughout a cycle, then when V(L) is high, I-avg(L) is also high. (i.e. when the AC input voltage is near 90°).

I usually think of CCM as the low-distortion option, but what limits BCM from also providing very low distortion? You know, because by looking at your waveform, it seems to be tracking that flat top AC with very little distortion, and without any "current loop" (per say).

[T3sl4co1l]

The adjustable range is fairly small, mainly I think because, at the low end, the "comparator" (Q8) shunts Q10, forcing a high-duty, high-frequency mode.  Probably just a matter of offsetting ranges, maybe a diode in series with Q9-C so it doesn't pull down all the way, and a resistor or diode below R15 for the same purpose.  Likewise, the high range is limited by Q8 Vebo and the ramp rate.  I suppose for the supply and load(s) I have here, 1.5 or 2.2nF for C6 would be fine.

Then it would be stable enough, and have adequate range, to hook up an error amp, and actually regulate output voltage over a range of load currents.

The on-time is indeed quite stable; here's a short gif of it:

https://imgur.com/gallery/UORIGSC

BCM indeed needs no current sense; it's a natural consequence of the method.  One for limiting or fault protection (per cycle, or for limiting input current or power as the case may be) might still be desirable.  In which case, the waveform might suffer; but I've seen controllers that keep a clean waveform, which are probably limiting the timer setpoint instead of terminating the cycle early.

BCM fails when, for very short on-times, most of the energy stored in the inductor goes into charging node capacitances and thus isn't reflected as power drawn from the source / delivered to the load, and so zero-crossing distortion arises.

Notice the rise and fall edges are segments of one continuous free ringdown waveform; normally the top is severely clipped (and stretched out in time) by the boost diode, but at lower and lower amplitude, relatively more time is spent in the edges and less in diode conduction, until at amplitudes below Vout, the diode doesn't conduct at all, and the waveform is basically that of an unclamped class E stage.  In that case, the switch either returns inductor energy to the supply via body diode, or by synchronous rectification (only difference is how soon a new on-time begins following the edge).  Thus, little input power is drawn either.

CCM certainly seems to be popular; though the economy of powder cores may be part of that?  It can be low distortion, but depending on type, emissions can be much worse (i.e. at very low frequencies, for FM/PPM types e.g. ST L4984; did a consulting project with that a few years ago, had to add an input filter DM choke to address the strong LF content), and some sort of hack is inevitably(?) necessary to handle DCM operation (kind of the central conceit of anything CCM that's not forced full-wave, really*).

(*And even then, you pay in terms of light-load efficiency.)

Anyway, BCM can be compensated, I think by using something like a ReLU function on some reference minus the input voltage, and adding that to the timer setpoint -- that is to say, artificially lengthening the pulse width at low voltage, proportionally below some threshold, so as to account for the switching node capacitive energy.  This is my guess what e.g. UCC2806x family's "crossover notch reduction" mechanism is; though it seems simple enough I don't get why they wouldn't put it on the -5 (which I guess doesn't have it?).

Tim

[magic]

How is the Chipageddon affecting you, DIY edition


How are control loops on those things done?
It would seem they can't have too much response at line frequency, or they would react to output ripple and become constant power rather than unity PF converters.
OTOH, they have to somehow deal with load steps and things like that...

[T3sl4co1l]

How is the Chipageddon affecting you, DIY edition

There indeed might be some merit in these sort of projects... but I'm not holding my breath.  In particular, it takes a lot of logic to address supply range, startup, shutdown/fault, etc. modes.  Even with basic chips involved, you'll likely end up needing much more than the usual riser board, even if it's populated with microscopic (SOT723s, 0402s or less, etc.) parts.  Nevermind the assembly cost from those hundreds of parts.

The outer voltage loop goes something like, 100k into 2.2uF feedback, with a zero resistor in series and a smaller 2nd pole capacitor in parallel with those ((Cp1 + Rz) || Cp2).  Or if gm amp type, then ~10µS into a shunting network of same.

That handles the low bandwidth (cutoff of some Hz).

Overshoot is usually managed by hackery: gm can be increased at the extremes (giving an 'M'-shaped gm function), or comparators pull in extra range, or there's clamping or shutdown on overshoot, etc.

When an inner current loop is used (CCM, some BCMs?), that's of course much faster, and compensated in the usual way (may be internal) (or not at all when peak or hysteretic mode).

Tim

[TimNJ]

The adjustable range is fairly small, mainly I think because, at the low end, the "comparator" (Q8) shunts Q10, forcing a high-duty, high-frequency mode.  Probably just a matter of offsetting ranges, maybe a diode in series with Q9-C so it doesn't pull down all the way, and a resistor or diode below R15 for the same purpose.  Likewise, the high range is limited by Q8 Vebo and the ramp rate.  I suppose for the supply and load(s) I have here, 1.5 or 2.2nF for C6 would be fine.

Then it would be stable enough, and have adequate range, to hook up an error amp, and actually regulate output voltage over a range of load currents.

The on-time is indeed quite stable; here's a short gif of it:

https://imgur.com/gallery/UORIGSC

BCM indeed needs no current sense; it's a natural consequence of the method.  One for limiting or fault protection (per cycle, or for limiting input current or power as the case may be) might still be desirable.  In which case, the waveform might suffer; but I've seen controllers that keep a clean waveform, which are probably limiting the timer setpoint instead of terminating the cycle early.

BCM fails when, for very short on-times, most of the energy stored in the inductor goes into charging node capacitances and thus isn't reflected as power drawn from the source / delivered to the load, and so zero-crossing distortion arises.

Notice the rise and fall edges are segments of one continuous free ringdown waveform; normally the top is severely clipped (and stretched out in time) by the boost diode, but at lower and lower amplitude, relatively more time is spent in the edges and less in diode conduction, until at amplitudes below Vout, the diode doesn't conduct at all, and the waveform is basically that of an unclamped class E stage.  In that case, the switch either returns inductor energy to the supply via body diode, or by synchronous rectification (only difference is how soon a new on-time begins following the edge).  Thus, little input power is drawn either.

CCM certainly seems to be popular; though the economy of powder cores may be part of that?  It can be low distortion, but depending on type, emissions can be much worse (i.e. at very low frequencies, for FM/PPM types e.g. ST L4984; did a consulting project with that a few years ago, had to add an input filter DM choke to address the strong LF content), and some sort of hack is inevitably(?) necessary to handle DCM operation (kind of the central conceit of anything CCM that's not forced full-wave, really*).

(*And even then, you pay in terms of light-load efficiency.)

Anyway, BCM can be compensated, I think by using something like a ReLU function on some reference minus the input voltage, and adding that to the timer setpoint -- that is to say, artificially lengthening the pulse width at low voltage, proportionally below some threshold, so as to account for the switching node capacitive energy.  This is my guess what e.g. UCC2806x family's "crossover notch reduction" mechanism is; though it seems simple enough I don't get why they wouldn't put it on the -5 (which I guess doesn't have it?).

Tim

Thanks for the explanation. Makes sense - I've definitely read some of that before, just you know, trying to get mud to stick to a wall (my brain).

Side note, we once modified a BCM design to reduce harmonics for LED lighting, and part of the solution was to reduce the capacitance of the CLC pi-filter after the bridge. IIRC, since capacitors have a leading phase angle, they want to draw current ahead of the input voltage. But, with a bridge "in the way", there will be a period of time where the capacitor current wants to draw current ahead of the input voltage, but it cannot because the bridge is reverse biased. Or, it was something to do with the DC side capacitors holding up the voltage so that the bridge diodes cannot be instantaneously flip-flopped between reverse and forward bias...Maybe those are the same thing.

So, BCM inherently needs a lot of filtering to keep the input ripple current/EMI down, and by virtue of that, you will also get some of these distortion issues.

Interesting point about CCM having potentially worse emissions. You would think, that the generally smaller peak-to-peak currents in CCM would mean lower EMI, by and large. On the other hand, CCM is fixed frequency so you don't get any sort of frequency spreading like you do with BCM. Or what were you thinking the reason was?

[T3sl4co1l]

Ah, good point.  That works here:



IS, RECT, this time on sample mode so you see the full ripple (give or take aliasing).  Cap after FWB.

Cap moved before FWB:



Indeed it's pulling down further inbetween.

(Note again, this is with an iron core transformer for supply, far from an ideal source.  So its LL and R will be a significant part of the response, and the cap is indeed quite important here.  Also, probably not far off from the impedance after a LISN + CMC, in terms of a more practical example.)

There's also an unavoidable notch simply because the FWB loses a couple volts; that's pretty apparent here, but not as important at real line voltages at least.

CCM, I think can be done a few ways -- the case I saw was obviously adapting frequency, I guess to force CCM even at low input.  Fixed frequency ones should be okay, yeah.  And BCM will be worse than FF CCM, on account of ripple being higher -- but for similar operating frequencies, for that reason only.  And multiphase much better still (of course!).

Tim

[SiliconWizard]

I was hoping you had used seven transistors for this one, but there are more.

[T3sl4co1l]

I was hoping you had used seven transistors for this one, but there are more.

Me too. Alas, I didn't see a way to remove quite so many at the time.   Perhaps it can be optimized down, though!  Almost certainly not once a full auto-restart thing and error amp are included though... ah well.

Tim

[magic]

I wonder if you could trigger on the drain going lower than the boosted output?

It should yield about the same timing under regular operation.
It could solve your startup and zero crossing problems, I think.

Switching losses will increase because more of drain capacitance energy will be burnt by the FET rather than regenerated to C1 (ideally you should trigger on the first valley following diode turn-off), but what the heck, maybe simplicity is worth something too.

[T3sl4co1l]

Easy solution to that is delaying the turn-on by approx. the 1/4 wave period.  Which, the propagation delays here already get pretty close, as you'll notice.

Voltage must always return somewhere between Vout and Vin, so a threshold somewhere in there would be a possibility, yeah.  That's kind of what the R4 bias does (though it depends on Vin because it's a divider).  Would also need/want some schmitt trigger and/or edge trigger logic, to make sure it triggers at all for startup, and doesn't override a preferably reset-dominant flip-flop.

Tim

[pardo-bsso]

I really dig your protoboard, and how you managed to not melt it in the way

[T3sl4co1l]

Look again beside the 22 ohm resistor...   But, for this very old (and brand name!) board, one accident isn't a bad record at all!

Tim