Not something you see every day:
https://www.seventransistorlabs.com/Images/Discrete%20BCM%20PFC.pdf- PoC. Not "commercially ready". Do try it yourself, critique, and improve. (Rules/goals? Generally I like to prefer transistors as much as possible for discrete designs; stuff like TL431 / op-amp / comparator, logic gates, etc. being acceptable when the complexity is just too bothersome to build out otherwise.)
- Input voltage and output current range are fairly narrow, haven't put much thought into it yet as far as why, or how to improve it
- Output voltage regulation not implemented (control input (R15) is trivially replaced with an error amp, once range issues are addressed)
- It really works! At least in the range that it does, input current tracks input voltage, giving high PF.
- ...I don't have a measure of PF, but check the waveforms, they're not too bad, considering.
Principle:
When a boost converter is held in BCM (Boundary Conduction Mode: inductor current just returning to zero as the next cycle begins), and when it is charged with a constant on-time, then input current is proportional to input voltage, and high PF results. We then merely vary the on-time to vary the output power.
Circuit explanation:
Q10-Q11 form the gate control latch/flip-flop. Q12, Q4, Q5 form the gate driver (inverting, with CCS + emitter follower pull-up, and relatively strong pull-down from Q12 via D11). Logic is implemented with a current-sourced RTL, or I2L, sort of scheme: R8 and R9 bias the collectors up, and either that current flows into the collector, or the various bases wired in parallel. It's not actually I2L because the base resistors allow me to cheat and get actual fanout. Voltage swing is small and speed is quite reasonable.) The pull-up currents are reused by the timer and driver CCSs.
On the left, pulse timing. While Q7 is on, FFNQ is low, so CT is allowed to charge slowly through Q3. When the voltage rises a Vbe above Q8's base, it shunts the pull-up current, diverting it to Q10, flopping the flip-flop; thus a monostable timer is made.
On the top, quasi-resonant feedback. When SW dips down below RECT, Q2 is forward-biased, emitting a pulse to TRG. Q6 gates this pulse (dependent on FFQ) to start a new cycle. Thus it's a monostable with retrigger, and that works to operate in BCM.
The cycle doesn't restart reliably: at low input voltage in particular, there isn't enough signal to trigger Q2. In this case, and also for startup in general, an external source (function generator, V2) provides stimulus, and Q1, level shifting. (Also as a result, there's zero-crossing distortion, i.e., little current is drawn at low input voltages; this probably only costs a few percentage points of PF.)
Since the power source is just a spongy little 12V 600mA transformer, little is needed for a power stage -- a relatively large inductance to get Fsw ~ 100kHz, and a mere IRF510 and 1A diode will do. C5 is very overkill, just happened to be handy. EMC improvements are indeed shown: the relatively long lead length of C5 was found to be excessive, and the combination of a drain FB (L2 is actually threaded onto Q7's pin), plus local bypass C4, got that under control. Increasing gate resistance, or FB on G or S, was found to have relatively little effect, at relatively high expense to switching loss -- for example for R10 at 100-220Ω, is enough to get rid of the ringing, but switching is rather sloppy.
Input waveforms: RECT (Ch.2, top) and IS (Ch.3, bottom). 10x probes, so that's 13V, 150mA input. Classic flat-topped power here, but current is following that just fine as it should. As you can see, a lot of zero-crossing distortion, where Vin isn't enough for Q2 to trigger on, more or less.
This is at 30V output, so 2.7W. 13V * 0.15A = 1.95W... uh well, hmm, don't worry about that huh...
That's better... DMM says AC input is 14.5V and 207mA RMS (3W at PF = 1). Not sure why the rectified values don't match..?
Zoomed on the leading edge. There's some fluctuation in what phase the switching starts at, but this is a typical example. You can clearly see the slow rising and sharp falling edge, due to the large boost ratio at this point; and that it goes to zero, or maybe slightly reverses (hard to say from here, but at least stray inductance shouldn't be a big source of error, at these currents and rates), as we expect for BCM.
Zoomed near the peak, also half horizontal scale to get a better look at the waveform. The extra spikes are due to the switching edge coupling through; without EMC measures, this was a taller, wider tone burst (ringing). Now they're short enough to even alias at this sample rate. (In Peak Detect mode, the turn-off transient shows up to 4 div peak; turn-on is less than a div -- which more or less confirms adequate BCM operation is achieved.)
And zoomed even further, gate waveform (at G3). Rise and fall are nice and sharp, preshoot I think comes from Cdg (again confirming BCM or something near it), and... not sure actually how it undershoots at turn-off, doesn't seem like that should be an inductive effect.
I have one component on the breadboard, not shown on the schematic: a 4.7k from G3 to GND; this is so I can break gate drive (e.g. remove R10) to disable the output. The turn-off looks normal (returns to 0V more or less immediately) without it. Huh. B-E recovery (storage) in Q5 maybe..?!
And drain waveform (SW), here delayed to 1.6ms hence the more modest levels; the quasi-resonant recovery is basically just rail-to-rail, and a small blip accompanies turn-on.
Tim