power decoupling myths

[Siwastaja]

Question: are capacitors with reverse geometry any better for decoupling? I concluded that, unless it helps to minimize track lengths, it doesn't matter. So, it should help if supply pins close to each other, but it is pointless if supply pins are far. But I've never checked this. Any opinions?

Obviously, you'll be able to squeeze the loop area a bit smaller. A small optimization.

The availability, cost, and uncertainty in second-sourcing weigh more, I'm afraid.

For general-purpose IC decoupling, this doesn't matter; you can use a 100nF 0201 for example, reversing it makes very little difference.

In power electronics with large C values this could be beneficial, though they have larger loop area caused by larger semiconductors as well so the capacitor is still a small part of that. I use quite a lot of 1206 parts when I need around 48V busses, 0805 is quite marginal, both for voltage ratings available, and amount of actual capacitance available under the DC bias. 1206 has a stupid shape, and 1210 is too big alraedy, so I'd prefer say a 0909 or 1010 instead, but the real-world availability of the parts is what drives the decision.

On the other hand, with 1206, I'm able to place additional vias for both pads under the component body, while avoiding via-in-pad. For reverse geometry, I would definitely need via-in-pad in order to exceed the performance of the 1206 design.

[TheUnnamedNewbie]

Question: are capacitors with reverse geometry any better for decoupling? I concluded that, unless it helps to minimize track lengths, it doesn't matter. So, it should help if supply pins close to each other, but it is pointless if supply pins are far. But I've never checked this. Any opinions?

I think one of the bigger advantages can actually be placement, instead of loop area. The impedance is lower, because not just the loop area on PCB, but also internally in the capacitor, the plates are shorter and wider, which gives you lower ESL.

Murata had a document showing how a 'reverse geometry' cap can give you higher denstiy, because when you align them with pins, you have the narrow side of the cap near the chip. (image source: https://www.murata.com/en-global/products/capacitor/mlcc/smd/lll)

[exe]

Murata had a document showing how a 'reverse geometry' cap can give you higher denstiy, because when you align them with pins, you have the narrow side of the cap near the chip. (image source: https://www.murata.com/en-global/products/capacitor/mlcc/smd/lll)

Huh, this rises even more questions . One is, in another thread recently people concluded that if two ICs are that close, then they can share the same decoupling cap. Sorta what murata proposes, except that there is no need to use fancy caps. What do you think?

And another question that bothers me a lot. A common best practice is to put a decoupling capacitor for each power pin. I often have one LDO supplying power to multiple ICs. Question: can these caps start resonating with each other? Or should I use a separate LDO for each potentially noisy IC? To be more specific, my typical scenario: MCU, ADC (with two power rails: analog and digital), and digital isolator on the same board.

[TheUnnamedNewbie]

As I've stated a few times now, it's really impossible to make any hard guidelines. If you want to be really safe, it is likely easier to get good noise isolation by having separate LDOs for each. ADCs (or general mixed-signal chips) are a whole different can of worms with people giving contradicting advise on how to do things in terms of decoupling and supply noise. One of the issues there is that you have currents that might want to flow from the analog supply to the digital ground and vice-versa, so your loop area becomes massive for those currents. (incidentally, also why so much on-chip stuff goes differential for those applications - you have no high-frequency common-mode noise, so less common-mode noise issues)

[T3sl4co1l]

Huh, this rises even more questions . One is, in another thread recently people concluded that if two ICs are that close, then they can share the same decoupling cap. Sorta what murata proposes, except that there is no need to use fancy caps. What do you think?

"that" close = ?

If they are slow logic or analog ICs, locality of bypass won't matter.  Example: CD4000 logic, TL072 amps.  There simply isn't any energy or gain at frequencies high enough to matter; bypasses can be inches away.  (If even that: historic example, the NES controller used a, CD4021 I think, and that's literally all that's soldered to the board.  No bypass caps, just a long cable with +5V and GND, clock, strobe and data.  The controller buttons are carbon-rubber pads touching gold plated traces, and the pull-up resistors are screen-printed ink!)

74LS and HC are fast enough you'll want a cap within a few inches, but the chips being smaller than "a few inches" means a few chips can probably share.

74LVC and most <= 3.3V CMOS devices (MCUs, etc.) are fast enough that you probably want the local-at-the-pins bypass caps, and not only that but if you have heavy loads on them (e.g., MCUs and bus drivers can switch a few 100 mA at a time, through whatever combination of IO and power pins).  Wide-format capacitors may be advantageous.

The best use-case is where a plane wave needs to be shunted to ground.  The plane wave propagates along a wide transmission line or plane.  It goes into the capacitors broadside (as many lined up in parallel as needed to cover the width of the plane), then into vias to ground (arrayed opposite the plane, along the C's GND pad).

There probably aren't many practical cases where this exact situation arises...

Most loads are through narrow pins, traces or vias, and there are simply a lot of them, and not always in regular patterns.  So the best you can do is sink them all to planes, and bypass the planes at the earliest convenience.  (Example: most any device that has to be a BGA, is probably also fast enough to need immediate bypassing, but also has to be connected in this way, i.e. through an array of vias.)

A resonant stub, in RF circuitry, I think is a good example, and some have been pictured earlier in this thread I think.  The vias, capacitor and trace are all accounted for in the total length of the stub, and the trace width is held constant thanks to the wide (appropriately chosen) capacitor.  So there's no error due to lumped equivalent whatever.

And another question that bothers me a lot. A common best practice is to put a decoupling capacitor for each power pin. I often have one LDO supplying power to multiple ICs. Question: can these caps start resonating with each other? Or should I use a separate LDO for each potentially noisy IC? To be more specific, my typical scenario: MCU, ADC (with two power rails: analog and digital), and digital isolator on the same board.

Can they?  Perhaps.  Draw the equivalent network and see if it does.

See, your very next question must be: what information do I need to figure it out?  Well, you don't have resonance without L and C.  What are the stray L's in the circuit?  What resistance dampens it?  What transient loads/sources might excite it?  And then you can answer these, quantitatively, by inspection of the circuit, build a model, and test it.

Tim

[David Hess]

And another question that bothers me a lot. A common best practice is to put a decoupling capacitor for each power pin. I often have one LDO supplying power to multiple ICs. Question: can these caps start resonating with each other? Or should I use a separate LDO for each potentially noisy IC? To be more specific, my typical scenario: MCU, ADC (with two power rails: analog and digital), and digital isolator on the same board.

Yes, it is possible, and it can be calculated with transmission line length, loss, and impedance but this is not always easy.  The impedance mismatch between the transmission line and decoupling capacitors causes reflections and if the Q is high enough, they become a problem.  One solution is to properly terminate the transmission line.  Lossy ferrite beads or RLC decoupling can be used to decrease Q which has saved me a few times before I understood what was happening.

[exe]

I let myself ask another question or two about decoupling and noise .

Is it a common practice to use, say, series resistors on digital lines? I once did an experiment: I breadboarded an spi digital isolator. When I probed the signal there was massive ringing (thanks to long jump wires). I installed 1K resistors in series and all ringing was gone. Why 1K? Values much bigger than that increased rise time too much for the data rate.

Strangely enough I almost never heard of this method of reducing digital noise. Only in one datasheet for an LT ADC there was a suggestion to put up to, afaik, 150 Ohm resistor. Values bigger than that were discouraged because digital inputs had some sort of protection from slowly rising signals, or something like that. I don't remember what part was that, but, e.g., datasheet for ltc2420 also mentions serial and parallel termination of digital lines.

I've also seen a small series resistor (1-2 Ohm) before ldo and its input capacitor. This, presumably, should reduce noise from fast-switching load back to the power rail. Is this a common practice? If not, why?

[thm_w]

Is it a common practice to use, say, series resistors on digital lines? I once did an experiment: I breadboarded an spi digital isolator. When I probed the signal there was massive ringing (thanks to long jump wires). I installed 1K resistors in series and all ringing was gone. Why 1K? Values much bigger than that increased rise time too much for the data rate.

Strangely enough I almost never heard of this method of reducing digital noise. Only in one datasheet for an LT ADC there was a suggestion to put up to, afaik, 150 Ohm resistor. Values bigger than that were discouraged because digital inputs had some sort of protection from slowly rising signals, or something like that. I don't remember what part was that, but, e.g., datasheet for ltc2420 also mentions serial and parallel termination of digital lines.

Its not terribly common, because the device would work without them (unless we are talking about high speed signals 200MHz+), the benefit is for noise as you say in specific situations. eg TI suggests doing this for their 24-bit ADCs. Or if you were driving a chip thats a long distance on the board and worried about EMI, it would be worth adding. Otherwise, why add them? Build your circuit on a PCB and see if there is much ringing.

"TI recommends placing 47-Ω resistors in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, DRDY, RESET and START). This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines"

I've also seen a small series resistor (1-2 Ohm) before ldo and its input capacitor. This, presumably, should reduce noise from fast-switching load back to the power rail. Is this a common practice? If not, why?

Sometimes this resistor is for additional power dissipation reasons. Normally you'd use a ferrite bead for noise suppression.

[T3sl4co1l]

Jumper wires on breadboarding will be in the 150-300 ohm range; a comparable size resistor will control the ringing.  Loose wires make poor transmission lines, expect lots of coupling between groupings.

The general term is "source termination resistor", for which you should find a lot of information I would think.

Ferrite beads are useful for the same purposes, for similar reasons -- at ~100MHz they offer significant resistance (per the rating).

Tim

[exe]

Can you advice me on which ferite beads to use? From what I read, there is always a danger of resonance between ferite beads and decoupling caps. Would it help to use the beads with the biggest dc resistance? (I bought some with 2 Ohm beads, but never tried them in action). I work with low-power stuff (dac, adc, mcu) and my concern is noise injection into analog circuitry.

[T3sl4co1l]

Again, for what?  This is not a cut-and-dry situation!  If you need simple answers, just bypass it and be done; if you find problems, spin the board with more filtering.

Tim

[David Hess]

Can you advice me on which ferite beads to use? From what I read, there is always a danger of resonance between ferite beads and decoupling caps. Would it help to use the beads with the biggest dc resistance? (I bought some with 2 Ohm beads, but never tried them in action). I work with low-power stuff (dac, adc, mcu) and my concern is noise injection into analog circuitry.

I have never heard of that happening with ferrite beads because they are designed to be very lossy, but I have had it happen with low loss inductors which would have been more suited for a switching power supply.  The solution to that is a parallel resistor across the inductor to lower the Q and this decoupling configuration is common in old test equipment between assemblies.

At a low enough power, RC decoupling becomes reasonable.  A ferrite bead normally only provides a couple hundred ohms so if the current draw is low enough for a couple hundred ohm or larger resistor, just use the resistor.

[exe]

If you need simple answers, just bypass it and be done; if you find problems, spin the board with more filtering.

Making new boards is what I'm trying to avoid . My current approach is to add a footprint for the bead. If it's not needed I'll just put a zero-ohm resistor.

[Siwastaja]

If you need simple answers, just bypass it and be done; if you find problems, spin the board with more filtering.

Making new boards is what I'm trying to avoid . My current approach is to add a footprint for the bead. If it's not needed I'll just put a zero-ohm resistor.

Note that if you are doing one-offs, say, less than 5pcs, it's likely a more optimum configuration to skip that footprint altogether and just bodge when necessary. Optimum in terms of the big picture, that is.

This is because 95% of the time, you don't find any problem and don't need to add the bead, so you end up soldering those jumper resistors by default. All of this is extra work in schematic, layout, and hand-fabrication you need to do every time, for every unit.

Instead, I tend to design in what I expect to be the final configuration, then if I missed something or measure an unexpected problem, I bodge it to the PCB, cutting a trace and adding a ferrite bead somewhere is not too difficult if it only happens 5% of the time.

Generally, I have been reducing the "trying to think about every possibility beforehand" mentality, reducing placeholders, extra prototyping features etc., because I found out I rarely have time to try and measure every possible thing I thought would be nice-to-have beforehand. And when I do have a problem, it happens to be something I did not expect to see... So I try to make prototypes as close as the final product as possible, then work around the limitations when necesssary.

Number of cases I have needed to re-spin a prototype PCB (something serious enough that it can't be bodged): 0.

But this is just my €0.02.

[electrolust]

https://www.picotest.com/products_Decoupling_Test_Board_Kit.html#gsc.tab=0