"Swinging" inductor for CCM PFC

[TimNJ]

Hi everyone,

Here's the situation. I'm working on a CCM PFC stage, currently using an RM10-size ferrite core inductor. There is a stringent line harmonics requirement that we are trying to meet, which drove the decision to use CCM in the first place. Transition-mode (TM) is much more typical in this power range (~120W), for a "normal" application.

The efficiency is pretty good, and actually very much optimized at this point. I went through the whole switching loss vs Rds-on optimization thing, and we've tried many different MOSFETs to try to find the sweet spot.

But, I'd really like to get another 1% efficiency, if possible.

I've seen many commercial power supplies with CCM PFC stages use a Sendust or moly-permalloy (MPP) core, instead of ferrite. These converters can typically get away with a lower switching frequency, which gives way to lower switching loss. With a high enough magnetic field intensity (current through the inductor), the permeability begins to roll off, but gradually, unlike ferrite. Depending on the load, the permeability of these cores can "swing" from high to low, and back to high again, during one 60Hz mains cycle. This can be advantageous for CCM converters, but I still can't exactly wrap my head around why!?

I've seen several references to swinging inductors in CCM PFC controller application notes, but never a detailed design procedure, or at least a solid explanation of the theory surrounding them.

Here's one app note, for example: https://www.infineon.com/dgdl/Infineon-ApplicationNote_PFCCCMBoostConverterDesignGuide-AN-v02_00-EN.pdf?fileId=5546d4624a56eed8014a62c75a923b05

Can anyone point me to any good resources on swinging inductors for this application?

Thanks!

[NiHaoMike]

At what load level are you trying to optimize? At light load, gating off the drive signal at low instantaneous input voltage will give the best results.

[T3sl4co1l]

Big downside is the variation in loop speed and gain, which at least shouldn't be much (the swing is only ~3x for reasonable construction and materials?) but may contribute to distortion, who knows.

I never felt convinced that a swinging choke really makes any difference.  AFAIK it's an old fashioned minor cost saving measure.  You still need the turns*area to handle the waveform, and maintaining inductance is just a matter of a little more wire and gap.

Tim

[TimNJ]

At what load level are you trying to optimize? At light load, gating off the drive signal at low instantaneous input voltage will give the best results.

We are trying to get improvement at 50-100% load. (That's a pretty big range, I know. Maybe we can call it "75%".)

Do you mean gating off the transistor completely near the AC zero crossing? Or some sort of burst-mode?

Thanks!

[TimNJ]

Big downside is the variation in loop speed and gain, which at least shouldn't be much (the swing is only ~3x for reasonable construction and materials?) but may contribute to distortion, who knows.

I never felt convinced that a swinging choke really makes any difference.  AFAIK it's an old fashioned minor cost saving measure.  You still need the turns*area to handle the waveform, and maintaining inductance is just a matter of a little more wire and gap.

Tim

That's an interesting perspective that is seemingly contrary to a few app notes and designs I've seen. Maybe it's an idea that's been passed down over time without much thought about why?

Still, let's suppose we have a 3mH inductor at no load. What advantage is there if this inductor looks like 1mH inductor at full load, peak of the AC wave? How and what does that help you with? Maybe you can "get away" with using a smaller inductor by allowing partial saturation for a portion of the AC wave. But, I would imagine harmonic generation will be worse while the inductance is down..

Thanks.

[T3sl4co1l]

I guess it's as surprising as ones' opinion of appnotes.  I find they're filled with hear-say, outdated rules of thumb and a distinct lack of analysis, so that would be par for the course. 

(Not saying I have any more confidence or insight on this particular subject, mind.)

Tim

[DannyTheGhost]

Okay, I'm just trying to make theories without any good proofs.
In cases when you get too much inductance you won't be able to achieve desired output voltage at full load.
You have two choices from here - lower inductance down or operating frequency.
But in case of these "inductors" you get less chances for this kind of situation to occur when you're getting closer to full load.
I hope I didn't sound too dumb

[jbb]

OK
There are a few ways to break the stalemate. It depends on what you want/need.

1) Have you tried a Silicon Carbide (SiC) diode in your switching stage? A carefully selected one could be very helpful because it reduces reverse recovery losses and MOSFET switch on losses.

2) Does reduced inductance values cause excessive THD (or specific harmonics)? If so, it might be possible to deploy a more advanced control algorithm using a microcontroller (eg use a PLL to find the mains waveform fundamental, then a set of resonant PI controllers to bring harmonic currents down to zero). But this will cost board area and firmware development time.

3) Moving to a Silicon Carbide or Gallium Nitride (GaN) power switch gets you to a completely different region of switching loss vs RDSon characteristics. You may be able to push up the switching frequency, reduce the inductor size and improve efficiency at the same time.

[T3sl4co1l]

Okay, I'm just trying to make theories without any good proofs.
In cases when you get too much inductance you won't be able to achieve desired output voltage at full load.
You have two choices from here - lower inductance down or operating frequency.
But in case of these "inductors" you get less chances for this kind of situation to occur when you're getting closer to full load.
I hope I didn't sound too dumb

This is true for DCM though.

The OP states CCM.  In CCM, inductance sets current ripple; duty cycle sets voltage ratio, and output current divided by voltage ratio sets input current.

Tim

[TimNJ]

OK
There are a few ways to break the stalemate. It depends on what you want/need.

1) Have you tried a Silicon Carbide (SiC) diode in your switching stage? A carefully selected one could be very helpful because it reduces reverse recovery losses and MOSFET switch on losses.

2) Does reduced inductance values cause excessive THD (or specific harmonics)? If so, it might be possible to deploy a more advanced control algorithm using a microcontroller (eg use a PLL to find the mains waveform fundamental, then a set of resonant PI controllers to bring harmonic currents down to zero). But this will cost board area and firmware development time.

3) Moving to a Silicon Carbide or Gallium Nitride (GaN) power switch gets you to a completely different region of switching loss vs RDSon characteristics. You may be able to push up the switching frequency, reduce the inductor size and improve efficiency at the same time.

Thanks for those ideas. We are already using an SiC diode.

I haven't done too much testing regarding the relationship between inductance and line harmonics, but am pretty confident a higher ripple current will make the situation worse.

We have not tried SiC or GaN MOSFET. I haven't seen many people doing this. Any "simple" reason why?

Thanks.

[jbb]

Yep. They cost more :-)

SiC MOSFETs may need a bit more gate drive (eg 18 - 20V, see device datasheets). Also, the standard TO-220 and TO-247 packages aren’t good because their lead inductances compromise the switching behaviour.


GaN devices are generally a little trickier to drive, depending on the types used. You could start with some searches.

[NiHaoMike]

We are trying to get improvement at 50-100% load. (That's a pretty big range, I know. Maybe we can call it "75%".)

Do you mean gating off the transistor completely near the AC zero crossing? Or some sort of burst-mode?

The gating trick probably will not be effective at high load. It works at light load by not running the converter when its efficiency is low, but at higher load, the increase in RMS current will likely undo any efficiency gains. It also would be limited by the power factor target at load levels where it applies.