OLD thread update:Please let me know if my very-high-power load has a fatal flaw

[Davidwasalreadytaken]

I put an update in the last comment.  tl;dr: I blew it up and rebuilt it

Attached is the schematic.  I have started building this but before I get too far down the road I would like some input from the community.  It works in LTSpice but I haven't run it yet IRL. I am using some DIP-specific perfboard for the small signal bits and I know there may be some concern with oscillation but that will have to be discovered when I actually get her all put together and under test.  There will obviously be some heat coming off this especially at high voltages, but I have about 17lbs. of heatsink for that and I can easily go bigger.  I usually won't be putting high power through for very long, and it will be fan-cooled so I *may* be ok with heatsinking.

R33 is for current sensing, pulled from a defunct Agilent power supply. To be used with a digital panel meter for live indication of current input

There will be a bipolar +/-15V supply for the opamps, and I intend to take my reference from that.  R34 eats most of the voltage, R35 and R36 are coarse and fine current adjustment potentiometers. 

The current goal for current is about 8 amps per FET, limited by the 3 Watt 0.05 ohms sense resistors between each 47N60C3 and ground.  I think that should be enough current for most of my needs (!) but the FETs can go quite a lot higher.

Opamps I think will work are LT1007 https://www.analog.com/media/en/technical-documentation/data-sheets/LT1007-LT1037.pdf
Nice low offset for use at the very low voltages required for control at low current

The MOSFETs are 8 pieces of 47N60C3 https://pdf1.alldatasheet.com/datasheet-pdf/view/428753/INFINEON/47N60C3.html
TO-247 650V, 30A @ Tc 100ºC, 415W

The polarity protection diode is 300UR60A http://www.vishay.com/docs/93508/vs-300urseries.pdf
Giant stud mount, 600V 300A
I ran 80 amps through this and it got warm but not hot, maybe 55ish C on the case, so I may not heat sink this.

[Gyro]

I am using some DIP-specific perfboard for the small signal bits and I know there may be some concern with oscillation but that will have to be discovered when I actually get her all put together and under test.

You will probably want to put the 150R resistors directly on the Mosfet gate pins - or better still, split them into two resistors, one at the opamp output, one at the Mosfet, to prevent the opamps seeing too much capacitive load too.

You haven't said what the source voltage is going to be (although you have mentioned plenty of high voltage parts). You need to keep a close eye on the 47N60C3 SOA graph to make sure they don't suffer breakdown when operating in linear mode (they look like to be optimised as fast switching fets).

[Yansi]

You better put a cap from the inverting input to the OPAmp's output, rather then splitting the gate resistor in two, which I'd say is very likely not necessary.

[Vovk_Z]

47N60C3 have to be ok for linear mode. And yes - a 2.2nF..4.7nF cap have to be from output to inv. input.
And consider much more powerful FDL100N50 (but not too expencive) - it may need less transistor cases than with 47N60. It costs only a little more then 47n60 but can withstand up to 1000W per case.

With lt1007/1037 don't forget to use Vos trim circuits for every opamp to adjust its input offset (or some transistors will be partially open with zero control voltage).

[schmitt trigger]

Your basic circuit looks ok.

My only comment would be that your control voltage to be derived from a proper reference IC.
Even the inexpensive and ubiquitous TL431 will provide a significant set-point improvement.

And start thinking about the protection circuits. Fuses, voltage clamps, thermal shutdowns.

[Davidwasalreadytaken]

@ Gyro I will have to keep an eye on things.  The layout is going to be fairly tight (for veroboard) but I may end up having to do something else with gate resistors.  The voltage is going to be possibly even over 100V in to this.  I have another active load but it is only good for a fraction of an ampere at 100V which is a bother testing high voltage supplies.  I get heebie-jeebies thinking about playing with higher voltages but it's nice to know most of my parts won't turn to smoke at expected voltages.

@ Yansi that's another possible avenue to pursue.  We'll see how necessary it ends up being but thanks for the idea!

@ Vovk_Z the transistors were selected mostly due to their being the highest-power MOSFETs I have on hand for $0, which is currently the cost of this build to date with all parts already acquired!  Having never seriously dealt with trimmable opamps, I was under the impression that I could leave the trim connections open.  I can't measure microvolts and these are guaranteed to have microvolt-level input offsets, so I don't know how I would go about measuring or correcting it at that level.  Do you have any good tips for that?

@ Schmitt trigger the control voltage does not have to be precise for my application.  As long as the reference is something like stable it will be good-enough even if it needs tweaking during use.  If I were controlling this with a microcontroller I would *definitely* agree that a known-stable voltage was present from which to derive a reference!  Protection circuits may or may not be coming.  I am thinking about a thermal overload that will at least pull the gate drive away from all the FETs if I somehow get distracted and things get too warm.  I'll think about fuses, but I don't even know what I might do with a voltage clamp, what do you mean by that?

Thanks all for your consideration!

[SiliconWizard]

As far as heatsinking goes, just consider all the use cases. Depending on the load, @8A, each transistor may have to dissipate a lot of power. Not completely sure about what you intend to do with this though.

[Jay_Diddy_B]

To the OP,

I would add a capacitor around 1nF between the non-inverting input and the output of each op-amp.

This will be the dominant pole that controls the loop stability.

You should also add a RC snubber on the input probably 2.2uF and 1 .

If you want to know all about loop stability in constant current loads read this threads:

https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/

Loads of information in this thread.

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,

This SOA graph from the datasheet:



Is probably not reliable information.

reference:

https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20100014777.pdf

These look like calculated curves. Measured curves show a thermal instability region at high voltage and low current.

I would test one or two MOSFETs in the linear region.

What is the specifications you are aiming for?

Jay_Diddy_B

[Kleinstein]

The MOSFETs are quite large and would this need quite some capacitance at the OPs to slow them down.
So one may not really get full speed from the LT1007. Even larger MOSFETs would make things even worse.
I would no use so much voltage for the OPs - 10 V would be plenty and less risk to overly stress the gates.

Power ratings for MOSFETs tend to be specified too high to be real - to avoid to much effort with cooling, I would consider more like 100 W the maximum useful limit per TO247 case.

The SOA graph looks suspicious, though Infineon usually is honest with the SOA graphs. IT still looks really good - maybe to good to be true.

For the shunts, one should not use the full nominal power, as this would lead to quite some heating and thus drift. So I would consider more the 3-4 A the useful maximum for 0.05 Ohms 3 W shunts.
This would be only some 150-200 mV, so the dynamic range to lower currents is somewhat limited.
I would consider using only 1 or 2 channels for lower current ranges.

For the current sharing also take care about the interconnections near the shunts - these should be balanced. This can also add to the current. For higher accuracy consider 4 wire connections to the shunts, even if only 2 wire parts.

A nasty case to consider is that it takes some time for the MOSFETs to turn down, when the electronic load is turned on before the external supply is connected. This would especially a problem with a high supply. Ideally one would have some protective circuit to turn off the load, once the voltage drops below some 1 V. Another countermeasure would be limiting the OP / gate voltage to a level not much higher than actually needed - this may need an adjustment. Chances are some 4 V would be enough.

[Davidwasalreadytaken]

@ SiliconWizard, I am anticipating blowing off nearly a kilowatt on this at high voltage and high current inputs.  That is ok with me.

@ Jay_Diddy_B I will have a look at the linked information, thanks for that.  I know the SOA looks like a calculated one, but I hope most of the potentially-unstable region on the very top is going to be outside my intended use range anyway.  I don't have a specific set of desired input parameters, just "as much as I can reasonably sink without blowing up".  The idea is to characterize it after assembly by giving it increasing static input levels and seeing what the temperatures do.  If it only gives me "a whole lot" instead of "crazy level" input power I'll likely be happy.

@ Kleinstein Speed is not my concern, these are to be adjusted by hand and I think they should be "close enough" during my anticipated normal operation.  How worried should I be about the gates? They are looking to be run well under their maximum ratings, possibly well under half.  The 0.05 ohms resistors are heatsinked also, but I will run current through them to see how warm they get before making a final call on how much power I can get from them.  In the worst case I can just use higher power resistors.  For lower current I have a nice Kikusui load which is fully self-protecting and more convenient to use in any event.  I am trying my best to make sure the conductors are similar lengths, and the 'ground' references taken from the same place.  Please elaborate on the 'nasty case', I am not sure what you mean about turning down the mosfets.  The way I have been using my loads to to make sure everybody is at minimal voltage and current settings, power supplies and loads, before connecting and powering on (and when shutting down).  Also this load is for use with self-limited power supplies, so I think presenting a very heavy load at turn-on should be somewhat less dangerous than otherwise

[Zero999]

What's the minimum load voltage required for this to work? Can you burn more power in resistors, rather than transistors?

Oh and if you're interested in simulating a potentiometer using LTSpice, I did a tutorial awhile back which you might find useful, even if it isn't for this project.
https://www.eevblog.com/forum/beginners/simulating-potentiometers-using-ltspice/msg2358510/#msg2358510

[magic]

The marketing "power dissipation" numbers are quite irrelevant, particularly for high power parts. Instead, look at thermal resistance and permissible junction temperature and do the math.

Don't forget about case-to-sink resistance, which appears to be the primary limiting factor with very large FETs, assuming that those "typical" numbers I collected from various appnotes but never really tested myself are anything to go by:

Code: [Select]

TO264  .15 K/W
TO247  .21 K/W
TO220  .40 K/WThe above table really cooled my enthusiasm for 2kW devices with .0x K/W specs.

Regarding offset voltage, it really depends if it's positive or negative. If at least one opamp ends up regulating its IN- to slightly higher than its IN+, you will never be able to get the current down to absolute zero. A simple solution to that is to allow the IN+ voltage to go slightly below ground. Furthermore, between any two sections, current imbalance will be equal the difference of their opamps' offset voltages divided by 50mΩ.

edit

Please elaborate on the 'nasty case', I am not sure what you mean about turning down the mosfets.  The way I have been using my loads to to make sure everybody is at minimal voltage and current settings, power supplies and loads, before connecting and powering on (and when shutting down).

It's simple. If the load is set for 1mA current but there is no PSU and therefore 0mA current, the opamps will apply full 15V to the gates. There will be a high inrush current until the opamps recover from saturation and discharge the gates down to the linear region. If the PSU has too much output capacitance perhaps the FETs may blow up, if its short circuit protection isn't as good as you think perhaps the PSU may blow up

So far I have had luck operating such unprotected load myself. It is, however, naturally limited to some 150~200% nominal current by base resistor and beta droop of the power BJT.

[Vovk_Z]

In any case, there has to be an offset correction circuit. It depends only on opamps TS will use - precision with dual supply or usual with a single supply.

[David Hess]

High currents through the low side returns between the current sense resistors and ground point is going to add errors and with so many sections in parallel, symmetrical wiring will be difficult.  An alternate configuration where each operational amplifier is connected deferentially to its current sense resistor will remove the effects of the circuit wiring.  Think of how it could be done with 4-wire current sense resistors.

Opamps I think will work are LT1007 https://www.analog.com/media/en/technical-documentation/data-sheets/LT1007-LT1037.pdf
Nice low offset for use at the very low voltages required for control at low current

A slower part like the LT1001 would be more suitable.  The least expensive single precision part is the OP-07 and the LT1013 and LT1014 are the least expensive precision dual and quad parts because they are multiply sourced.

Even with a slower part, some external frequency compensation may be required for best performance.  If expense is not an issue, then I might use a precision part which supports overcompensation like the LT1012 or LT1097.

A higher performance design will require buffers between the operational amplifiers and MOSFET gates to better drive their input capacitance.

[Jay_Diddy_B]

High currents through the low side returns between the current sense resistors and ground point is going to add errors and with so many sections in parallel, symmetrical wiring will be difficult.  An alternate configuration where each operational amplifier is connected deferentially to its current sense resistor will remove the effects of the circuit wiring.  Think of how it could be done with 4-wire current sense resistors.

Snip ..

Hi<

1+

This is how HP did it their high power loads:




Schematic provided by forum member MarkF in this thread:

https://www.eevblog.com/forum/projects/yet-another-diy-electronic-load/msg2460276/#msg2460276


Regards,
Jay_Diddy_B

[Davidwasalreadytaken]

@ Zero999 there is no minimum load voltage specification really. 5V is probably as low as I would use it, but it has been simulated ok down to 2V.  IDK how it would do at low voltage on the bench.  Thanks for the tips on making a potentiometer, but I find for myself it is instructive to be changing resistor values or voltages directly. It helps me to think more clearly about the circuit.

@ magic if I don't get absolute zero current input that will be ok for my intended purpose.  Even a large fraction of an ampere would be fine but I would like to be "close" to zero.  The 'nasty case' . . . that's potentially pretty bad!  The voices tell me I should be able to switch something to ground before turn-on to make sure everybody is on the same page.  I will have to think about this a bit . . . the method HP used on the schematic linked by Jay_Diddy_B seems pretty clever.

@ David Hess the low side of the sense resistors are the 'star' grounding point and the sense wires come from immediately on the other side of the body of the sense resistors.  I don't know how much closer I could get than that.  Symmetrical wiring is one of the aesthetic design goals, and it seems pretty elegant that it is also a functional goal!  The only 4-wire sense resistors I have handy in quantity are 0.01 ohms and I am not sure I want to go that low.  They are rated for much more power but I don't think I will need that.  The choice of opamps was dictated by parts on-hand as I am currently at $0 of my $0 budget for this item, so I am going to have to make them work but thank you very much for the suggestions.  If I end up with instability I will try the above suggestions to cure it first, but adding a pre-driver stage of amplifiers is now on the list so thanks for that too.

@ Jay_Diddy_B that is fascinating, thank you. I was wondering how the others were thinking to get a 4-wire measurement and that explains it nicely.  That is something like double the complexity of my current idea and with David Hess' idea I'm heading on up to 3x complexity!  If I can get by with my simpler circuit I will do but if I find it doesn't work as expected you guys are definitely giving me lots to consider.  Using that sense circuit seems like it would make things more reliable if I wanted to use my 4-wire 0.001 ohms resistors.  The TurnOn circuit is interesting and seems to obviate the 'nasty case' magic was talking about.  If I read this correctly, the gate drive is low enough to keep the FETs off until the diode is biased out of the way.  Is that right?  Blessing be on that color-highlighted schematic!

The service manual with explanations is here https://www.keysight.com/en/pd-1000001519%3Aepsg%3Apro-pn-6060B/300-watt-dc-electronic-load?pm=PL&nid=-536902299.536880312&cc=US&lc=eng for anyone may want that

[Vovk_Z]

if I don't get absolute zero current input that will be ok for my intended purpose. 

- It isn't very ok, because it will turn transistors fully on if there isn't a connected DUT power supply. Then if you connect it live - you'll have a sparks and can weld wires. So it is better to have a comparator or something which will turn the load off (automatically or not).
I used a comparator, look at my attachment (but there is no need in VT2).

[Davidwasalreadytaken]

Is that driving the outputs of the opamps low in the absense of a current signal? I could sit down and figure it but a hand-wave overview in a sentence would be welcome!  I wonder what you think of the scheme used by HP as posted above by Jay_Diddy_B as an alternative?

[David Hess]

High currents through the low side returns between the current sense resistors and ground point is going to add errors and with so many sections in parallel, symmetrical wiring will be difficult.  An alternate configuration where each operational amplifier is connected deferentially to its current sense resistor will remove the effects of the circuit wiring.  Think of how it could be done with 4-wire current sense resistors.

This is how HP did it their high power loads:

Wow, they used an instrumentation amplifier for each sense resistor.  That is sure one way to do it.

What I might do is generate a positive compliance reference current for each section (1) and use this to drive a precision resistor tied to the negative side of each 4-wire current sense resistor producing the reference voltage for that section.  Now when high current through the ground return raises the low side of the sense resistor, it raises the low side of the reference resistor by the same amount.

(1) This is easier and cheaper to do than it may first appear.  The impedance of the current source only has to be higher than the resistance of the high current return wiring to provide error cancellation so a voltage source driving multiple precision resistors to make a divider with the reference resistor is sufficient.  So it requires half of the resistors of the instrumentation amplifier implementation and no operational amplifiers or maybe one.

[coppercone2]

test it in a steel box

Maybe a used PC tower that you put hinges on

all the analysis does is save you money, the test is going to be critical

[David Hess]

@ David Hess the low side of the sense resistors are the 'star' grounding point and the sense wires come from immediately on the other side of the body of the sense resistors.  I don't know how much closer I could get than that.  Symmetrical wiring is one of the aesthetic design goals, and it seems pretty elegant that it is also a functional goal!

It seems that you have it well in hand  then.  The remaining problem with the wiring is that the 600ppm/C temperature coefficient of the copper wiring degrades the precision of the current sense resistors.

If I end up with instability I will try the above suggestions to cure it first, but adding a pre-driver stage of amplifiers is now on the list so thanks for that too.

It is easy enough to add a feedback capacitor from the output to inverting input of each operational amplifier to limit bandwidth if that is necessary.  Gate drivers would be required to support higher bandwidth.

[Kleinstein]

The turn off part in the HP schematics seem to hard turn down the gate drive. This looks like brute force, driving the OP into there maximum output current. The actual control (e.g. comparator) is still not shown.


One way to avoid driving the gate all the way to saturation would be to add a limit to the effective resistance. So the current set signal should not be larger than a fraction of the MOSFET drain voltage. This would effectively make a kind of the constant resistance more that takes over ones the voltage gets to low. Practically one would likely have a divider for the set point signal and clamp the voltage before at a slightly larger level (e.g. some 2-5 V full scale).
In addition there should be some offset so that 0 current can actually be reached.

[Vovk_Z]

Is that driving the outputs of the opamps low in the absense of a current signal?

Yes, I'm about that.

  I wonder what you think of the scheme used by HP as posted above by Jay_Diddy_B as an alternative?

- it's a pro way. I've seen that. If you need something very durable and can afford some complexity and have physically enough space - of cause it is better. My circuit is for a small simple low-power (50-200 W) device with an ATX-case size.

[Jay_Diddy_B]

Hi,
I measured the input current on an HP60501A, essentially the same circuit.

Reproduced from this thread:


https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg2725614/#msg2725614

Let me start with a little benchmarking. I will display the test results for an HP 60501A (150W) load module in a 6050A mainframe. The load is set to the 3A range and 1A constant current mode.
The current was measured with a Tektronix TCP202A DC current probe.
The power supply used for the testing HP665A set for 5V and 2A limit.

Test 1



This is using the ON/OFF button on the power supply.

Test 2



This is 'hot-plugging' the power supply into the load.

Note: the current scaling was changed from 200mA to 500mA/div


It would be interesting to see the results for testing other popular electronic loads for example B&K, Rigol, Maynuo etc.. I don't have any of these.

Jay_Diddy_B