I've worked a bit in comms so I am at least familiar with the terms you used.
For an ADC the numbers you provide would give you only about 5.5 bits. You can bump that up to 7 bits if you use a PLL to generate a ~100 MHz clock for the ADC circuit, ~8 bits with a 200 MHz clock. The limitation will be the I/O cells themselves. Rising and falling edge asymmetries and high/low drive level asymmetries will distort the average value of the feedback signal, at some point dominating as the rate increases. You can also gain one bit of resolution for each halving of the data rate from the ADC. So you might ask yourself if you really need a 50x ratio between the ADC sample rate and the control PWM rate. I'm not sure what you would do with that data unless you are extrapolating curves.
The ADC I am working on is sampling at 33.55 MHz but with a very low data rate, so lots of decimation and averaging. The counter is 18 bits, so the other end of the scale from what you are doing.
Just as a point of comparison, the audio output from the device I am working on uses 32 kHz to produce audio tones. Seems they like their alarms to not be alarming, but rather musical.