Hand-soldering on a 4Oz/140um PCB?

[sparkydog]

Have you paid attention to your creepage requirements?

Yes, but only for 240VAC (340V peak).

Yeah, I was confused about this, too, so I asked. IIUC, you only need to spec for kV if you're trying to design your board to actually withstand a lightning strike. Otherwise, you just need to insulate the project as a whole, so that a spike won't arc over and kill a person that happens to be near it.

OTOH, clearance may be 3 mm, and you don't get the really small creepage unless you can assert that you're Pollution Group 1.

And I was working with IPC-2221B (only because the Saturn PCB calc didn't use 62368-1 and I didn't yet understand the difference.

It seems hard to find clear calculators for 62368-1 (presumably professionals just have the spec itself and don't need to use them). I've found a few, e.g. this and this (my understanding is that UL60950 and IEC 62368-1:2023 match up to 30kHz), but they aren't clear (to me) re: internal vs external layers, how to handle coated vs uncoated traces, etc.

I think the requirements are the same, at least for your usage. That said, you can at least check the draft. (I really, really hate standards organizations that charge you an arm and a leg for a standard you have to follow, especially for safety standards. There ought to be laws against that.)

Creepage for 250V is 0.56 mm if your board is sealed against dust and condensation, up to 4 mm if it isn't.

In this context does "sealed" include internal layers and top/bottom traces under solder mask? If so, I meet both of those (well, after resetting the pad sizes on the connector to the factory size).

Unclear, but my guess would be that it doesn't matter, or rather, at best you can add the layer thickness to your actual creepage.

[prosper]

May I ask what it is about the four-layer duplicated-traces method that seems unwise? Is it the ambiguity about thermal dissipation with the power traces on internal layers? Like even though I'm meeting the IPC-2152 numbers I'm still kinda cutting it close, so why not go simpler and just have some burly bus bars or wires to make it a non-issue?

Reason I ask is that I have the board all ready to go and was juuuust about to pull the trigger when these last two replies came in. If I'm being dumb I can suck it up and do yet another re-design (don't want to get lost in a sunk cost fallacy) but it seemed like I had finally gotten my head straight about the trace widths, separation, etc., so I was feeling ready to go...

Just personal preference. I like to avoid 4-layer designs if I can (i.e. for simple circuits). Unnecessary cost and harder to bodge / prototype on. Plus, as you noted, buried traces have more complex thermal characteristics to consider. Busbars are just simpler and cheaper.

[chconnor]

Thanks! Very interesting reading. I don't envy professionals that need to thoroughly understand that spec, but I do respect them. :-)

I'm a little surprised that 62368 doesn't seem to distinguish at all between internal/external layers, and between coated/uncoated traces. I can believe that at 240VAC you can't trust the solder mask to be rated to isolate that voltage from direct contact, but it seems like it should be relevant to trace separation, at least a little. And surely internal traces buried in the board should have milder requirements? I'm also remembering the drastic differences that internal/coated/uncoated are granted under 2221B (0.25mm, 0.8mm, and 2.5mm, respectively. That said, I suppose 2221B is obsolete for some good reasons.)

As you noted, maintaining 4mm everywhere on the board, whether internal/external/coated/uncoated or pins is going to be tough... e.g. the connector pin pad edges are 4.3mm apart, so a trace of any significant width is going to bring that under 4mm. I'm using an HCPL3700M IC which feeds what for me peaks at 170V (rectified 120VAC) out to two pins that by 62368 are supposed to be 2mm apart (bare minimum 1.4mm at the most relaxed) but those pad edges are ~1.3mm apart (before a trace is even involved.) And that IC is rated for 240VAC as well... Seems like either I'm not understanding 62368 yet or they assume you will conformally coat if using ≥120VAC?

At any rate, my current plan, submitted for comment by anyone gracious enough to spare this newbie any more time:

- expose areas at the ends of the power traces
- solder appropriate-gauge coated wire to double those traces to act as additional current path (insulated and rated to appropriate voltage). (AKA bodge wires, but, you know, nice ones. :-) )
- remove power traces from the top layer (now that they are reinforced with the wires, and already doubled or tripled on the other layers, might as well not have the HV near the components on the top)
- conformally coat the bottom of the board on the high voltage side of the PCB
- add some high voltage transient suppression for the L1/L2/N feeding the stove (in the hopes of preventing high voltage spikes from even reaching the PCB, and allowing me to escape needing 6, 8mm clearances, etc.) (still researching details on this; e.g. not sure if this kind of thing will suffice.)

[uer166]

For traces buried in PCB, you're looking for a term called "cemented joint" in UL-world. I'm not sure about that IEC standard since I'm not familiar with it, but generally internal traces are handled very differently, and spacings can be much smaller given a few conditions are met.

Maybe search for "solid insulation" as well.

[chconnor]

Thanks -- I did see "solid insulation" in the draft 62368, and I'll check for "cemented joint" as well.