Phase comparator and PLL, ringing and overshooting

[Ken27]

Greetings

this is my first post on this forum. I have designed and locked a VCOXO from a reference signal of 10 kHz.
I don't have schematics at the moment,  I am using a CD4046 phase comparator Type 2.
Now, I would like to hear Your honest opinion about the possible reason for ringing locking as per attached screenshot.

I tought that phase margin can affect the locking time, but it locks in less than 3 second on the reference signal (GPS)

Since I can understand without schematics can be difficult to oversee possible problems, I will tell You I exclude the ground loop self-inductance of the probe which causes resonance leading to ringing, overshoots or undershoots after fast signal edges, even I am not using active probes at the moment.

Would like to know Your general recommendations an some theoretical formulation about possible hypothesis .

-- Edit

the upper track on all screenshot is the 10kHz signal from the GPS, the one below is the 10 kHz signal coming from a frequency divider , no MCU are used in this circuit.

[moffy]

The Type 2 phase comparator of the CD4046 is edge triggered and susceptible to noise, it is great for fast pull in with frequency differences but its lock will be noisier than the Type I, the XOR phase detector, because it will have to dither between leading and lagging to maintain lock. The XOR mixer will generally give a lower noise lock as long as it can successfully pull into the input signal.

[Ken27]

Hi,

yes but the Type 1 doesn't lock in frequency, only in phase, can lock on harmonics...phase can be 0-180 etc...

[moffy]

Hi,

yes but the Type 1 doesn't lock in frequency, only in phase, can lock on harmonics...phase can be 0-180 etc...

If a PLL is locked in phase then it is also locked in frequency. Phase shift depends on the offset frequency divided by the loop gain and there are ways to guarantee a fixed phase of 90 degrees by using an integrator referenced typically against Vcc/2. You can even adjust the phase shift with a fixed offset but that will effect the capture and hold range. Harmonics should not be an issue for a known 10kHz signal, you just narrow the range of the VCO and make sure its center frequency is within the capture range. You have to decide if phase noise/jitter is important, if so then the best choice is the XOR mixer.

[Ken27]

Thanks for your reply, but XOR doesn't have real frequency detection.

Probably I will need to simulate another filter and set-up a narrower bandwidth for the type 2 comparator.

[PCB.Wiz]

Now, I would like to hear Your honest opinion about the possible reason for ringing locking as per attached screenshot.
I tought that phase margin can affect the locking time, but it locks in less than 3 second on the reference signal (GPS)

If it locks in 3 seconds, the PLL part is likely ok. 
Any ringing on PLL will eventually decay, are you sure you are not seeing the GPS jitter ?
See the other GPSDO threads.
The GPS output on most units, is derived from 48MHz TCXO that is digitally-swallow locked, rather than an analog VCXO. (they save parts and use a cheaper oscillator)

That means whilst the average is precise, any edge can be off from ideal, by ~ 20ns.

Usually a longer lock time than 3 seconds is chosen, to filter that 20ns jitter to smaller fractions of ppm.

[Ken27]

Thank You. I forgot to mention that in the oscilloscope track 1 (upper one) is the GPS and the lower one is the reference from the VCOXCO.

If it has a jitter by its own, can be mirrored in the PLL? and why then looks like is locking on a ringing spur rather than the real rising edge of the reference signal? These are my doubts at least. If would be the jitter, it would still lock on the rising edge, maybe leaving few ns difference? I am a bit perplexed. 

[fourfathom]

yes but the Type 1 doesn't lock in frequency, only in phase, can lock on harmonics...phase can be 0-180 etc...

Thanks for your reply, but XOR doesn't have real frequency detection.

Just how far can you pull your VCOXO?  You are dividing the XO frequency down to 10 KHz for the phase comparator, right?  The XOR phase comparator may take longer to pull in than with the phase/freq detector, but it seems unlikely that it will be able to find a false harmonic lock.

If the loop bandwidth is too narrow then the XOR won't generate enough of an offset to bring the oscillator into lock.  This actually seems likely, and one reason for using the F/F detector.  But the XOR is not going to lock on harmonics with a typical VCXO.

[Ken27]

You are dividing the XO frequency down to 10 KHz for the phase comparator, right?

yes of course. The OCXO is 10 MHz originally .

I can understand that XOR type will not create problems like these. That would be easier for many point of view, but for this specific circuit i would like to have a perfect frequency detection hence XOR could not be considered as reliable . But the reason to be here is that I would like to understand the reason of why it lock on that  sort of ringing  and the quantization  on the rising edge of the VCOCXO  side as you can see from the screenshot .

[fourfathom]

But the reason to be here is that I would like to understand the reason of why it lock on that  sort of ringing  and the quantization  on the rising edge of the VXCO side as you can see from the screenshot .

To understand the rising edge difference you will probably have to show us the circuitry between the detector and the oscillator.  Many designs will require some amount of phase-offset to generate the needed tuning voltage.

Ringing is generally a function of the PLL loop damping.  Yours looks not too far off from a "critically damped" loop, which will have some overshoot.  If you want less overshoot you need to go towards an "overdamped" loop.  Any PLL design text or app note should cover this better than I can.

[PCB.Wiz]

Thank You. I forgot to mention that in the oscilloscope track 1 (upper one) is the external VCOCXO and the lower one is the reference from the GPS.

If it has a jitter by its own, can be mirrored in the PLL? and why then looks like is locking on a ringing spur rather than the real rising edge of the reference signal? These are my doubts at least. If would be the jitter, it would still lock on the rising edge, maybe leaving few ns difference? I am a bit perplexed. 

Those traces show a stable fixed offset and an edge relative jitter (the 'fat' rising edge on one trace is showing the ~20ns jitter I mentioned)
A stable fixed offset does not always mean a problem - it could just be delays in amplifier paths, or a needed phase diff to give a DC-correction output.
A CD4046 at 5V is not a fast part, data says tplh is 350ns for example at 5V 

[Ken27]

Thank You for your useful suggestion will investigate further.

[dietert1]

As far as i remember at 10 MHz the HC4046 works better than the original CD4046. Also TI have a HC7046 that supports lock detection. And one can use a separate voltage regulator for it in order to reduce noise from the supply.

Regards, Dieter

[Ken27]

Hello, as written in the first post, the comparator is working aat 10 kHz there with some dividers.

I will try to change the 4046 type and eventually update if any differences.

[Ken27]

Hi,

I changed the IC from CD4046BE to CD74HC4046 AE without touching the circuitry .

Looks like the 74HC series is performing much better than the other one, the ringing almost disappeared , locking time is the same and now looks like the difference in ns is smaller, confirming that can be jitter as looks like it is not locking on ringing , since is not present.
Mystery remains, but maybe I am getting closer to the solution ..   

[David Hess]

As far as i remember at 10 MHz the HC4046 works better than the original CD4046. Also TI have a HC4047 that supports lock detection. And one can use a separate voltage regulator for it in order to reduce noise from the supply.

Later 4046 implementations remove the dead zone in the phase/frequency detector.  I think the HC version does, and any 4046A versions?

Ringing is generally a function of the PLL loop damping.  Yours looks not too far off from a "critically damped" loop, which will have some overshoot.  If you want less overshoot you need to go towards an "overdamped" loop.  Any PLL design text or app note should cover this better than I can.

Exactly, the frequency compensation of the feedback loop does not have enough phase margin.  Either lower the gain or add phase lead for better settling.

I have seen some high performance designs where the loop filter had notch filters to remove the comparison frequency and harmonics so the loop filter did not have to be tailored to remove them itself.

[dietert1]

We don't know which of the two signals is jittery and 20 nsec is a lot of jitter for a crystal oscillator. Next step is to measure the VCO signal. The jitter may very well stem from the GPS receiver and disappear in the PLL. This is what the PLL is meant for.
For best results one should use a synchronous counter as divider for 10 MHz to 10 KHz.

Regards, Dieter

[Ken27]

We don't know which of the two signals is jittery and 20 nsec is a lot of jitter for a crystal oscillator. Next step is to measure the VCO signal. The jitter may very well stem from the GPS receiver and disappear in the PLL. This is what the PLL is meant for.
For best results one should use a synchronous counter as divider for 10 MHz to 10 KHz.

Regards, Dieter

Hello Dieter, as explained in the first post, both signals are 10 kHz (the one coming from the OCXO is divided)

I did a correction as the upper track on all screenshot is the 10kHz signal from the GPS, the one below is the 10 kHz signal coming from a frequency divider , no MCU are used in this circuit.

[dietert1]

Will you show the VCO control signal? Do you use a synchronous counter as divider?

[fourfathom]

Will you show the VCO control signal? Do you use a synchronous counter as divider?

The reason this can matter is that a ripple counter will have jitter accumulate at each divider stage.  A synchronous counter will not have this accumulation.   If the ripple counter delay timing allows it, you can add a single "D" register at the ripple counter output, and clock that with the input clock.  This will remove the ripple jitter. 

[PCB.Wiz]

We don't know which of the two signals is jittery and 20 nsec is a lot of jitter for a crystal oscillator.

True, but this is not actually measuring the crystal oscillator directly.

Looks like the 74HC series is performing much better than the other one, the ringing almost disappeared , locking time is the same and now looks like the difference in ns is smaller, confirming that can be jitter as looks like it is not locking on ringing , since is not present.
Mystery remains, but maybe I am getting closer to the solution ..   

Looks almost as-expected to me.

If you do a single shot capture, the jitter should not be present.
if we take a 48Mhz osc that is 2ppm off, and digitally correcting, that will do 96 corrections every second, so an infinite persistence capture will show the 20ns corrections.
I would expect distinct visual ~20ns groupings, but that also depends on your scope and filtering software.
Is the long term average looking correct ?  (stable DC voltage on the VCOCXO pin ?)

It would help to post a circuit of what you are testing.

[David Hess]

20 nanoseconds of jitter is pretty typical of a GPS frequency output when it is generated using direct digital synthesis.  The 20 nanoseconds represents the frequency of the clock into the counter.

[T3sl4co1l]

As far as i remember at 10 MHz the HC4046 works better than the original CD4046. Also TI have a HC4047 that supports lock detection. And one can use a separate voltage regulator for it in order to reduce noise from the supply.

Later 4046 implementations remove the dead zone in the phase/frequency detector.  I think the HC version does, and any 4046A versions?

I thought it was the other way around, HC never recovered the "glory" of the original's oscillator linearity and overlapping detector response?  Even the 7046, 9046(??) didn't quite achieve things?

Dunno, never used them myself; simply done very few projects where phase lock was required.

Tim

[Ken27]

Will you show the VCO control signal? Do you use a synchronous counter as divider?

The reason this can matter is that a ripple counter will have jitter accumulate at each divider stage.  A synchronous counter will not have this accumulation.   If the ripple counter delay timing allows it, you can add a single "D" register at the ripple counter output, and clock that with the input clock.  This will remove the ripple jitter.

Thanks all for answers. No, I am indeed using  asynchronous counters as dividers.
I will try with sync ones!

[dietert1]

Today i found this german blog entry about the 4046: https://www.elektronik-kompendium.de/public/schaerer/pll4046.htm
The person claims that the input pin 14 doesn't work reliably with a digital input signal. He found that there is an input amplifier meant for signals with 1 or 2 V amplitude and with sharp edges. Strange.

Regards, Dieter