PCIe adapter board - how many stitching vias is too much & more design questions

[Komajster]

Hello!
I just designed a board that will be hooked up to a very heavily modified laptop and will provide three external PCIe connectors. Basically, it's only an adapter board with barely any active components.


And I have three main concerns regarding it:
- did I use too much of ground stitching vias? Is there anything to worry about regarding that?
- it's a 4-layer board, the layer stackup starting from the top is as follows:
  1: signal traces and ground pour
  2: ground plane, no signal traces
  3: 12V power plane, no signal traces
  4: signal traces and ground pour
   I plan to install a high-end GPU in the PCIe x16 slot, the GPU can pull up to 75 W of power from the slot and probably generate some minor switching noise from the DC-DC switching regulators that it has, should I be worried about the PCIe traces running on the bottom layer (right next to the 12V power plane) getting some interference from that?
- https://0805.pl/uploads/pcie-adapter-board-2.png - Is this an optimal distance of ground pour to signal traces? Does it matter much? I also noticed that on some commercial designs they don't always make ground pours on exposed layers if there are internal ground plane(s), maybe I also should have only the internal ground plane?

Huge thanks for any advice!

[T3sl4co1l]

External pour doesn't matter very much as the edge-to-edge coupling is quite small.  You can if you want to, just check the geometry.  You're making differential CPWG.  Saturn PCB tools are good.

Routing over 12V plane is fine as long as it's well bypassed.  Sprinkle ceramic caps around the board, particularly near connectors.  They're serving the same purpose as the vias shown above.

BTW, the vias look fine.  They're not optimal, but it looks like they auto-placed more or less everywhere important.  Prioritize near connectors, at peninsulas, at crossings between layers (for 2-layer designs), and periodically along traces.  For this, the period should be a few mm.  So, the grid is fine.  It helps to look at the negative space between traces, and in multilayer designs of course you have to be mindful of what's on every layer when you place a via.  Just for the last reason alone, I tend not to use outer pours, as the gain is very marginal (little edge coupling) for so much work.

Tim

[ConKbot]

I'd make provisions for decoupling caps under the cn1/2/3/4 connectors, near where your layer changes happen. 'Ground' currents need to pass from your 12v plane to the gnd layer as you change layers.  Ideally you'd have one very close to each via pair,  but putting it between each pair of vias so one cap can service two pairs may work.  Same goes for other layer changes, but those are the easiest examples.  When i do a layer change for a high speed pair, I like to put via for ground planes close to the pair, but the necessity for a cap in your case limits how close in they can be.

[Komajster]

Thanks for the replies!
This might be a dumb question, but what caps should I use? Something like 1 nF, 10 nF or bigger?

I wanted to understand why the decoupling capacitors are needed near where the high speed signals change layers, so I found this article that proves the point: https://www.asset-intertech.com/resources/blog/2014/09/avoiding-stitching-vias-and-decoupling-capacitors-on-high-speed-signals/

common design practice is to employ reference plane stitching vias or decoupling capacitors whenever high-speed signals need to transition layers. This is because there must be a return current path for each signal, and this current must be returned on an adjacent power or ground plane. If the two such planes are at the same potential, a stitching via is sufficient. If they are not at the same potential, a decoupling capacitor provides the low-impedance pathway.

I also found this paper that tries to describe this in detail if anyone is interested: https://www.researchgate.net/publication/4037137_Coupling_of_through-hole_signal_via_to_powerground_resonance_and_excitation_of_edge_radiation_in_multi-layer_PCB#pf1
And I think that now I somewhat understand what is happening in there, but this explanation still feels a bit above my head (I'm just 17...  ), so if anyone knows about some YouTube video that explains this more graphically (for example, like Dave did in his EEVblog #859 - Bypass Capacitor Tutorial), then please let me know.

[T3sl4co1l]

Over 10nF will be fine, up to maybe a few uF to also get some filtering on 12V if that matters.  0.1uF is the don't-care go to.

Tim

[Komajster]

So I decided to go with 0.1uF 0402 caps (areas with them marked white to make them easier to spot):



There is some more bigger MLCCs under the PCIe connectors, but those I mainly intended for filtering.
Is there any other place where it would be nice to have a cap on?

Thanks for help!