Thanks everyone!
Next PCB preview attached. This is getting more and more out of my hands, most of the traces i am happy with but perhaps most important ones (SPI) are looking like a plate of spaghetti, i just cant avoid vias.... which further got me reading a lot more about signal integrity which the got me back to the start of this topic where it was explained that basically SPI is too slow to worry about signal integrity...
I still have to stich GND planes and sprinkle GND vias around as that seems to be the big issue with MAX7219 ICs.
so, i know i am repeating the question but would all these vias on SPI affect anything?
Again, vias are fine. The things that jump out to me are:
- At the Arduino: this is fine, the top three traces on the bottom layer are clearly better dodging that bus of LEDs. Well, arguably I guess. As long as their bottom-left ends make room away from the next two or three traces on the bottom, bottom ground can pour around them.
- The 5V trace, from the, I don't have a clue what it is, there aren't designators on here, at least that are visible at this scale -- from the terminal block, there's a large enclosed area between the two traces dropping down to supply two chip resistors. This makes an island of ground on the top side, which has to be stitched around to connect effectively. Easier to just pull the 5V route down by the resistors, eliminating that island, and now stitching only has to be either side of that row of resistors, and connector (BRIGHTNESS CONTROL SWITCH?), no problem.
- Similar may be for the, whatever they are, the two smaller 4-digit displays bottom-center, currently unrouted -- those two traces dog-legging to the bottom-left may be better paired with the other two going up, saving you from enclosing the whole display area with another ground island.
- Also, those driver chips could stand to be rotated or flipped, probably.
- And if those dogleg traces are part of the SPI bus, then, a better route for the bus might be: Arduino, big display, bottom pair of small displays, left pair of small displays, dot matrix, top left displays and matrices, top center large matrix, top right matrix and display, center right large matrix, right matrices, etc. Oh, or are those displays and matrices paired, maybe it's better to chain them in some logical or physical order. Or if you have the serial chain all planned out, just route it back and forth, it's a mess that's what layout is for, resolving connections and you have a ton of space to do that with, it's fine.
It's hard to tell what's going on without being able to see net names on everything, so I'm making assumptions and keeping it somewhat general here.
Tim