PCB Top and Bottom pour - GND and VCC

[elcrni]

hi guys,

I've been working on a custom PCB design for the past few weeks, months long hobby project for decoding and analysing atomic clock radio signal and displaying various data on 7 segment displays. PCB is going to be cca 35x40cm. Now i've been using EAGLE for a couple of years now but nothing of this size and so many MAX7219 ICs, and as i am close to finish the PCB design, i am not sure about the top/bottom pour... so the question is: should i/can i have one layer as GND pour and another as VCC (+5V) and would that be a smart idea... not sure about interference with MAX7219 lines, noise or whatever else, OR should i go with 2x GND layer and then just route the 5V signal where needed (needed on a lot of places on PCB)

Is it a usual routine/common practice to have GND and Voltage pours as 2 layers or i should always use GND on both.

Most of the components are SMD so there will be lots of vias anyway, which ever way i go on this one.

Many thanks for any help,
Alek

[tszaboo]

You can do it either way, it's not going to make too much difference.
The usual way to handle this is to use 4 layer boards, with inner planes dedicated to power and ground.
Why this is expensive for 1-2 boards, in quantity, this increases PCB price by about 50%, so a 2 EUR board becomes 3 EUR. And it passes EMC testing unlike the 2 layers boards.

Just keep in mind that eagle is a terrible software, and it won't give you any warning if you have a pour that's disconnected or hair thin.
So route both signals everywhere, with tracks. Then pour it.
When I do two layer boards (rarely) I keep most racks on top, and GND fill the bottom and Top. Route VCC with 1mm track. I jump the track to top whenever I can, and try to avoid having long tracks on bottom. So rather have 6 or 8 via in the track than a slit GND plane.

[T3sl4co1l]

Tl;dr no.

You should generally have about half the layers in the design, dedicated to planes.  You can use fewer at higher layer counts, when modest crosstalk is not an issue (e.g., most digital comms, but not precision RF).

So, for a 4-layer board, since the outer layers have stuff placed on them (assuming a typical mostly-SMT design), you won't get much coverage there, so inner layers it is.  And there are two inner layers, so you can do GND and one VCC (divided up between domains however you like).

For a 2-layer board, you can only afford one.

But it's worse than that, because even if you have single sided placement (all components on top), you inevitably must resolve crossings by switching traces to the bottom side, for at least a short length.  This creates a slot in the bottom pour.

And if we pour on top, we'll have even less density due to all the components and routing already there.

So what to do?

If we pour both, and add stitching vias between top and bottom, around any crossing, or around any span where there's a slot in the respective layers, and avoid routing on both layers in a given location as much as possible: we can keep the loop length to a minimum.  That is, the loop of ground surrounding any given point, on any given route.

We can make an observation: anywhere two traces cross (or a trace under a row of component pads, etc.), there is a void straight through both pours.  The negative space in both, is overlapping.  In the case of two traces crossing, the best we can do is three or four vias in the corners beside the intersection, keeping the loop size down to trace width + 2*clearance.  We should strive to minimize this loop area.

If we poured VCC and GND, we would find we inevitably need numerous connections (jumper traces) to both, from pins orphaned by other connections.  The impedance, from any given point to this combined reference plane, will be higher.  Bypass is easy enough at least, caps can be placed anywhere the two pours overlap -- but getting to them is the problem, and to get low impedance at a component, you're probably still going to need local bypass anyway.  (One of the advantages of 2+ planes, is being able to eliminate some bypass caps.  Appnotes try to play it safe, they won't recommend this -- but it is very reasonable option, when one takes the time to consider the power distribution network (PDN).)  But worst of all, we don't have an alternate layer to stitch against: every single trace, on either layer, is a complete and utter void in that entire plane.  Ideally perhaps we would place a bypass cap at every crossing -- but that will get obnoxious very quickly, not to mention expensive.  We should only need a bypass for every power pin say, or group thereof.  Perhaps we would stitch by using two vias and a jumper track on the opposite layer -- but this is very fragile, not to mention tedious.  (This is a good alternative in locations where it's the best option, but it's probably a bad idea to design a whole board this way.  Let alone maintain such a design.)  Whereas stitching vias can sometimes be handled by EDA tool alone!

So I recommend to route a 2-layer board as ground both sides, and the layer affinity can vary with area.  So, preferably most components and routing is on the top, but bottom routing or placement is perfectly acceptable as long as it's stitched as well as the top side placement is; and as long as both are as exclusive as possible (no overlap).  VCC should be routed point-to-point as any other signal, with point-of-use bypass, and other PDN considerations as applicable.  (A point-to-point chain topology will generally approximate a lumped-equivalent transmission line network, which is easily terminated with some resistance at one or both ends.  We don't want to draw DC current with those terminations, so an R+C is used.  Typically an electrolytic or tantalum capacitor with nominal ESR, or a ceramic with the ESR added in series as a separate resistor.)

Tim

[elcrni]

Many thanks for your help guys.

@tim, thanks for extensive explanation, some parts are not really clear to me as i am not an engineer but i think i understand the gist of it.

Now, i did not mention that my board is 2 layer, as most of my other boards, there was simply no need for 4 layers, or at least i thought there was no need.

4 layers production cost does increase the cost but i would rather have it done at a higher cost properly than waste money on 2 layers and have something that may or may not work.

Also, one perhaps important thing i did not mention is that i am using embedded Arduino2560 board so that makes it easier as not too many traces and paths on the PCB
bellow is my board design, i still need to add one more component but this is basically it. Board render at the top shows the top layer where all components are placed, therminals, 7-segment displays and a few LEDs are more or less the only things going through both layers.




To my untrained eye, this still seems doable on 2 layer board, but perhaps only one layer as GND or both as GND and then VCC routed as any other signal.

once again many thanks for help.
Alek

[tszaboo]

4 layers production cost does increase the cost but i would rather have it done at a higher cost properly than waste money on 2 layers and have something that may or may not work.

Oh, it is going to work. Very likely it is going to work.
The issue is this:
There is a huge difference between
1) something barely working and 
2) something properly designed.

1) will work with one specific power supply, if you don't have noisy CCFL lighting, and will disturb channel 1 on the radio.
Large portion of the open source designs online are 1). And they dont get properly tested. And you need a lot more knowledge to make something proper, than something work.

[elcrni]

4 layers production cost does increase the cost but i would rather have it done at a higher cost properly than waste money on 2 layers and have something that may or may not work.

Oh, it is going to work. Very likely it is going to work.
The issue is this:
There is a huge difference between
1) something barely working and 
2) something properly designed.

1) will work with one specific power supply, if you don't have noisy CCFL lighting, and will disturb channel 1 on the radio.
Large portion of the open source designs online are 1). And they dont get properly tested. And you need a lot more knowledge to make something proper, than something work.

Thanks for your reply!
Unfortunately, since i am not an engineer and will never be one, and since this is a hobby, i am afraid i will never be able to design circuits properly or up to high standard by any measures :-)
I am a bit of a perfectionist and i do want/like to do things better or at least up to some standard, whatever i do, thus asking questions and trying to learn as much as my free time allows, but again if i am investing time in something i would very much like to make it as best as possible.

Many thanks,
Alek

[Siwastaja]

It is true that designing on 4 layers is far easier if you have the same design complexity. 2 layers is cheaper to manufacture but takes longer (and requires more skill) to design if you are interested in signal integrity.

If you are a bit of perfectionist and don't need to save cost, nothing wrong ordering a 4-layer PCB. Route on the top and bottom. Then you are left with basically three viable options:
1) mid layers are GND and GND.
Power is routed on top or bottom.

2) mid layers are GND and Vcc.
Separate power routing is not needed. Decouple the GND and Vcc planes with capacitors sprinkled all over; Vcc works as an AC reference plane as well as GND. Note, the layer doesn't need to be completely one net. If your design has multiple supplies, you can segment the plane.

3) mid layers are GND and routing.
You still have a full ground plane which is great, and a third layer for routing, which is handy especially with two-sided SMD load eating up routing space in top and bot.

Do note though that either top or bottom ends up without a closeby reference plane, instead interfering with the third routing layer. For low-to-medium speed*, a few trace crossings usually isn't disastrous, but there will be some crosstalk.

I often end up with a hybrid; i.e., mostly use the inner layers as planes, but then in case of a difficult routing, I "borrow" a plane a bit and run a trace of two there. You can't do that with brain turned off; you need to look at what traces cross and understand there will be crosstalk if/when that happens. Doing limited distances helps, so that the layer is still mostly a plane, with only short tracks with no critical signals on the next layer at the same spot.

*) speed refers to the signal edge rate. A microcontroller digital IO pin can have quite fast edge even if you switch just once a day. Some have configurable IO speed; if not, adding some 47ohm series resistors at the driving end helps.

[elcrni]

Thanks guys, really appreciate your help.
Since the cost increase for 4 layers is not a disaster, i will go with 4 layer design.

Now

Oh, it is going to work. Very likely it is going to work.
The issue is this:
There is a huge difference between
1) something barely working and 
2) something properly designed.

believe it or not, this design works without any issues for a year now, on BREADBOARD :-))) and showing a rats nest of wires would give a heart attack to a professional.
Idea here was to finally get the design onto a PCB thinking i would eliminate most of the issues with loose wire connections etc.


@Siwastaja
Many thanks for a nice explanation.  As i would rather avoid sprinkling caps across the board, perhaps i will chose 2 GN planes in the middle and then route signals and VCC on remaining 2 planes.
OR
Could i go with GND as top layer (that way close to many components on top layer) and the route signals and VCC on remaining 3 lines. Would this effect anything in ways different than having a GND in one of the inner layers and then route on remaining 3 layes?


Many thanks,
Alek

[Siwastaja]

You need to "sprinkle" those capacitors anyway, regardless of whether the power distribution network is a full plane, or a tree of traces on a routing layer. Basically one per IC pin is typical. Of course you can do with fewer of them, it's just a simple rule-of-thumb.

Analysing power distribution networks rigorously gets quite complex.

You can use top or bottom as a ground plane if you want to, but if it's an uninterrupted plane, then you can't place SMD components there. Using mid layers as reference planes (ground or Vcc) leaves both top and bottom free for mixture of placing components and routing.

Routing in the same layer as the (SMD) components means significant reduction in vias because you often go with a trace from a component to another, you don't want to hop layers all the time for no reason.

Component placement is important. With proper placement, you minimize the need for long tracks and vias, a good SMD design "flows" naturally from component pad to another component pad with just enough distance to make building (possibly debugging) it easy, but no more.

[elcrni]

Thanks Siwastaja!

Maybe there has been a misunderstanding about caps, i already do have caps on every IC, if you look closely i have 2 caps per IC (plus ISET resistor), one ceramic 100nF and tantalum 10uF for decoupling, same goes for Atmega328 MCU.

Routing in the same layer as the (SMD) components means significant reduction in vias because you often go with a trace from a component to another, you don't want to hop layers all the time for no reason.

Component placement is important. With proper placement, you minimize the need for long tracks and vias, a good SMD design "flows" naturally from component pad to another component pad with just enough distance to make building (possibly debugging) it easy, but no more.

Yes, this makes perfect sense, so top/bottom routing and inner layer or both for GND.

Many thanks,
Alek

[elcrni]

just finished a test autoroute, seems like awful lot of vias and routs dont make a lot of sense either.



Trying to understand why did it choose bottom plane for routing MAX7219 IC to Through hole 7-segment displays, thus creating lots of vias, when this could have been done without any vias on top plane...

[mvs]

so the question is: should i/can i have one layer as GND pour and another as VCC (+5V) and would that be a smart idea... not sure about interference with MAX7219 lines, noise or whatever else, OR should i go with 2x GND layer and then just route the 5V signal where needed (needed on a lot of places on PCB)

On 2 layer PCBs one side is usually used for prevalent horizontal signal routing, another side for prevalent vertical signal routing. GND plane is on both layers stitched together with vias.

MAX7219 are quite noisy chips, so place more different decoupling caps near them. You do not need to populate them all right away.
Ferrite bead in series with supply may reduce EMI aswell.

You may also want to reduce slew rate of SPI interface by adding low value resistors in series.

[T3sl4co1l]

You may want to hand-route some things first.  Short, simple connections (nets with few pins, say 2 or 3) are unlikely to conflict with anything.  SPI bus is probably next.  It should be routed together (to keep delays similar), and yes as mentioned, every pin driver should have a source termination resistor at it.  If the MCU is the only source, then there; if you're getting MISO back from various devices, or there is multi-mastering, then that too.

Then auto-route everything else.  Take note of where it's generated lots of vias, and try to untangle and simplify things.  If you see a lot of nets crossing your SPI bus, consider swapping its layer locally to allow them to pass -- this can save vias and routing congestion, and the bus doesn't care about passing through a few extra vias.

Nets routing between local areas, if there are any other than SPI -- try to clean these up, maybe make a routing grid they follow, as if highways and on/off ramps where crossing.  Probably, that much detail isn't needed, just that it may be helpful to think in those terms while teasing apart the mess created by the autorouter.

Also, since you've settled on 4 layers, go through and check every power and ground pin -- the autorouter won't always make these as concise as they can be.  Don't be afraid to use vias liberally, you can keep noise down by keeping trace and via length down, and not sharing vias/traces with multiple power pins.  (It's fine to share, like, a run of adjacent pins on a given device, that often shows up when there's a fixed pull-up/down pin beside a power pin.  Inputs don't count.  Sharing two adjacent, or nearby anyway, power pins, isn't usually a big deal either, though there are reasons why they might be preferred on separate vias.)

Tim

[elcrni]

thanks guys!

You may also want to reduce slew rate of SPI interface by adding low value resistors in series.

Should this be placed once in SPI line, ie from MCU to the first MAX IC or between each MAX IC as well?
For all 3 SPI lines? Resistor value?

@T3sl4co1l,

Yes, i always hand route some lines first and then do extensive cleanup after autoroute. Autoroute is there just to save some manual labor i guess.

Thanks,
Alek

[mvs]

Should this be placed once in SPI line, ie from MCU to the first MAX IC or between each MAX IC as well?
For all 3 SPI lines? Resistor value?

It should be placed on all used outputs: MOSI, CLK, LOAD of your MCU and DOUT of all MAX7219 except the last one in the chain.
Value depends on the desired edge speed. MAX7219 has its own memory and does not require much of SPI bandwidth, so you can reduce SPI speed to 100KHz or even less and use 100-330 Ohm for termination.
 

[elcrni]

It should be placed on all used outputs: MOSI, CLK, LOAD of your MCU and DOUT of all MAX7219 except the last one in the chain.
Value depends on the desired edge speed. MAX7219 has its own memory and does not require much of SPI bandwidth, so you can reduce SPI speed to 100KHz or even less and use 100-330 Ohm for termination.

Thats great, thank you!

[T3sl4co1l]

Should this be placed once in SPI line, ie from MCU to the first MAX IC or between each MAX IC as well?
For all 3 SPI lines? Resistor value?

On each pin driver (output), by the pin.  Location matters!

Tim

[phil from seattle]

Hand vs auto routing.  For beginners, it is tempting to rely on autorouting.  The results are well less than pleasing though. And the Eagle autorouter (unless significantly improved over V7.7) is pretty bad. I found that if the Eagle AR can get to 100% on a board, hand routing it isn't that hard.  If you are at all serious, hand routing is a must.  For your board, I think hand routing will not be that hard - 2L or 4L.  Try routing the power lines by hand first, then the comm lines (I2C, it seems) and see what the AR does after that. But, I think you will be better served by pushing forward with hand routing.

Eagle is not a bad choice. I used it for 20+ years with good results.  But always hand routed. I switched to Kicad a bit less than a year ago, and won't be going back.  The "push" routing feature makes hand routing a lot easier. Basically as you route a trace, it pushes the other ones to make room so you aren't constantly rerouting/moving other traces. It about doubled my hand routing speed and reduced the strain I felt with Eagle. I'd recommend moving to Kicad though maybe not for this project. If helps that Kicad has no strings attached like Eagle does. And if you are getting boards assembled in china, Kicad's CAM beats Eagle's, hands down.

[elcrni]

Thanks Phil from Seattle!

Yes, for this one it will be china, i tried them for the first time a month ago and was quite surprised by results, but went with "premium quality" so that may have helped as well.
Again yes, seems like it will be most hand routing on this one.

One question now, since LOAD and CLOCK lines from MCU to MAX7219 are common, do i have to run these two from MAX00 to MAX07 or i can make shortcuts, for example MAX7219 number 07 (last in chain) is quite close to MCU, can i just run LOAD and CLOCK straight to last MAX or does it for any reason need to follow the path from MAX00 to MAX07?

Another question, this is my first time working with MAX7219 SMT mount, i've notice "tRestrict" layer preventing me to access pins on top plane so i need extra vias to go under the IC and then exit to top plane again... can i remove this restrict in footprint and just access the pins without vias?

Once again, huge THANKS to all of you, i have learned a lot today!
Alek

[mvs]

One question now, since LOAD and CLOCK lines from MCU to MAX7219 are common, do i have to run these two from MAX00 to MAX07 or i can make shortcuts, for example MAX7219 number 07 (last in chain) is quite close to MCU, can i just run LOAD and CLOCK straight to last MAX or does it for any reason need to follow the path from MAX00 to MAX07?

With reduced slew rate and SPI clock speed you can route your traces as you like. It is definitely not a high speed design.

Even if you run SPI at max speed (4-5MHz clock or 250-200ns clock period on AVR MCUs) it should be ok.

[phil from seattle]

Another question, this is my first time working with MAX7219 SMT mount, i've notice "tRestrict" layer preventing me to access pins on top plane so i need extra vias to go under the IC and then exit to top plane again... can i remove this restrict in footprint and just access the pins without vias?

I don't see anything in the datasheet about a restriction.  Eagle IC footprints often have a somewhat dubious origin. In the words of Ronny Reagan, Trust but Verify. And, I would trust the datasheet over an Eagle footprint every time.

As long as we are on the IC footprint topic, always dry test your board layout with real ICs to make sure your footprints are correct. This has saved me several times.  And, conversely, not doing so has caused me a wasted PCB run (money and, more importantly, time).

[Siwastaja]

Just don't autoroute. Just no.

[elcrni]

hi guys,
Thanks for the help.

With reduced slew rate and SPI clock speed you can route your traces as you like. It is definitely not a high speed design.
Even if you run SPI at max speed (4-5MHz clock or 250-200ns clock period on AVR MCUs) it should be ok.

Thanks!

I don't see anything in the datasheet about a restriction.  Eagle IC footprints often have a somewhat dubious origin. In the words of Ronny Reagan, Trust but Verify. And, I would trust the datasheet over an Eagle footprint every time.

As long as we are on the IC footprint topic, always dry test your board layout with real ICs to make sure your footprints are correct. This has saved me several times.  And, conversely, not doing so has caused me a wasted PCB run (money and, more importantly, time).

Yeah, i could not find anything in the datasheet but though it could be some rule or something i am not aware of.
As for the dry fit, hah, i though i was the only one printing a PCB/footprint onto paper and dry fitting :-)

Now onto the autoroute. How i did it so far is i would autoroute everything and then extensively touch up all traces up to a point where i'd adjust every single trace on the board. Autorouter in my mind was there to decide if and how many vias etc, but judging by your comments, a monkey could do better. This got me thinking last night, if i am adjusting every single or most of the traces, why not try and hand trace everything from the start, as many of you suggested. At the start this was a bit scary thought but after an hour i did some 25% of the board routed. Ok, it was relatively easy for first traces as there were no path crossing yet but i was happy with how it went. did some more reading and found an interesting article with basic set of rules (https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/1207-seven-habits-of-successful-2-layer-board-designers) basically everything has been more or less said here on this post but the article is a sort of a summary with a few photos to illustrate. Turns out i was making mistakes with overkill trace widths among other things.

there are still a couple more things i am not sure about:

1. What has a higher priority to go straight without vias, signal (SPI, MAX7219 to display...) or power? If signal is crossing the power, should i place vias on the signal, or it doesnt matter?
2. Is there a quick way to stitch GND planes so i do not have to place 2 rows 6-8 vias each row, one by one? or i could go with just one row 4-6 vias?

Thanks again for helping me out with this. I think i am ready for my first, half-decent board routing :-)
Will report back how it went shortly.
Alek

[exe]

Should this be placed once in SPI line, ie from MCU to the first MAX IC or between each MAX IC as well?
For all 3 SPI lines? Resistor value?

On each pin driver (output), by the pin.  Location matters!

Oh, wow, finally I see discussion on this topic. The idea to put a resistor to "slow down" digital signals came to me a few years ago, but I never seen anybody doing it. Is this a viable solution? I've only seen once mentioned in one TI or LT datasheet to put 10-33 Ohm resistors on spi lines. I wonder if I can put more, like 100 or 500 Ohm provided I don't need much bandwidth?

There are two objections to do so:
1) noise immunity, for me it's hard to say if 500 Ohm drive is a problem and what's typical hysteresis on input pins of ICs. (Why 500 Ohms? I did an experiment, 1K resistors were good-enough to drive an isolator at data rate of  8 kbit or so, so 500 Ohms should have provided some margin in that case).
2) The one I came recently. I heard (including in AoE) that slow transient can cause a shoot-through. Like in this doc: https://e2e.ti.com/support/logic/f/logic-forum/737694/faq-how-does-a-slow-or-floating-input-affect-a-cmos-device . Is this still a thing? I've only seen max rise time specification a couple of times. Most of the time I see "min rise time" specification, which I'm not sure why is there, but I don't care as my signals are slow.

How I came up with this idea: I played around with digital isolators from aliexpress and I was checking their specs (they are kinda expensive from distributors, so I decided to take the risk for my pet project, it's not for isolation from mains, it's to separate channels on lab power supply, so kinda not critical for safety). I noticed a lot of ringing when using even moderately long wire on a breadboard. I was able to remove ringing with a resistor.

[Siwastaja]

Oh, wow, finally I see discussion on this topic. The idea to put a resistor to "slow down" digital signals came to me a few years ago, but I never seen anybody doing it. Is this a viable solution? I've only seen once mentioned in one TI or LT datasheet to put 10-33 Ohm resistors on spi lines.

Of course, it's being done all the time everywhere. Maybe you have wrong keywords?

In any case, the term is "series termination", but such term would be used only when the R is tuned for quite "optimal response", you could say; this happens when the total driver impedance (CMOS IO pin Rds_on + external resistor) matches the characteristic impedance of the transmission line, which is by the geometry of the line (basically the ratio of the track width to the track distance from the reference (return path) plane). With exact matching, reflections are eliminated (but the signal is only valid at the receiver pin). If you use too little R, you see reflections and overshooting voltage.

You can also use too much R by purpose...

I wonder if I can put more, like 100 or 500 Ohm provided I don't need much bandwidth?

... which will obviously still kill the reflections, but this will indeed slow down the edge. When R starts going well beyond the transmission line impedance, it's likely easiest to analyse as simple RC circuit, C being the parasitic capacitance of the receiver pin and the track itself.

There are two objections to do so:
1) noise immunity, for me it's hard to say if 500 Ohm drive is a problem and what's typical hysteresis on input pins of ICs. (Why 500 Ohms? I did an experiment, 1K resistors were good-enough to drive an isolator at data rate of  8 kbit or so, so 500 Ohms should have provided some margin in that case).

It's quite obvious increasing the driver impedance by adding more R in series reduces noise immunity. If your target is to significantly slow down the transitions, you need to use high values of R because the C is very small (by design; the IC manufacturers don't want to slow you down). Solution: use larger C! Larger C in itself filters noise, and it also allows a smaller R to be used.

It's not unheard of to increase the robustness against noise by limiting the bandwidth of plain old single-ended voltage based digital signaling by RC filtering. I have done that successfully many times. Something like a 100 ohms, 470pF for RC=470ns works way better than 2.2kOhm, 20pF (parasitic C only) for the same RC time constant.

2) The one I came recently. I heard (including in AoE) that slow transient can cause a shoot-through. Like in this doc: https://e2e.ti.com/support/logic/f/logic-forum/737694/faq-how-does-a-slow-or-floating-input-affect-a-cmos-device . Is this still a thing?

Basically all modern CMOS digital logic input pins have a bit of hysteresis - not as much as proper "schmitt trigger" inputs, but enough so that slowly changing input signals do not become noise disasters, let alone cause large shoot-through currents. For example, microcontroller pins typically accept any arbitrary DC voltage within the rails for unlimited time - because the pins are shared with ADC, anyway. A very limited version of the "shoot through" happens, though; the inputs do consume more current at the intermediate state (which is why the digital input circuitry can be programmatically disabled), but nowhere near to cause any damage; this is usually only significant in low-power (battery-operated) applications, or when this small extra loading distorts a high-impedance analog signal.